SCI RX Interrupt select logic
BRKDT
RXRDY
SCIRXST.6
SCIRXD
TXENA
SCI TX Interrupt select logic
TXEMPTY
TXRDY
SCITXD
RXENA
SCIRXD
SCICTL1.6
RXERRINTENA
SCITXD
SCITXBUF.7−0
Frame Format and Mode
Even/Odd Enable
Parity
SCICCR.6 SCICCR.5
8
8
SCICTL2.6
SCICTL2.7
RXWAKE
SCIRXST.1
RXENA
SCICTL1.0
RXSHF
Register
TXSHF
Register
SCIRXST.5
WUT
SCICTL1.3
TXWAKE
1
SCIHBAUD. 15 − 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 − 0
Baud Rate
LSbyte
Register
LSPCLK
RXBKINTENA
SCICTL2.1
8
TX FIFO
TX FIFO Interrupt
TX Interrupt
Logic
TXINT
TXINTENA
SCICTL2.0
SCIFFTX.14
SCICTL1.0
RX Interrupt
Logic
RXINT
SCIFFRX.15
RXFFOVF
RX Error
To CPU
To CPU
SCICTL1.1
SCIFFENA
Auto baud detect logic
PE
OE
FEBRKDT
RX Error
SCIRXST.7 SCIRXST.5 – 2
TX FIFO_0
TX FIFO_1
−−−−−
TX FIFO_15
RX FIFO
RX FIFO Interrupt
RX FIFO_0
SCIRXBUF.7−0
−−−−−
RX FIFO_14
RX FIFO_15
8
Transmitter Data
Buffer register
SCITXBUF.7−0
Receive Data
Buffer register
SCIRXBUF.7−0
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Introduction
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SPRUI07–March 2020
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Serial Communications Interface (SCI)
Enhanced features include:
• Auto-baud-detect hardware logic
• 16-level transmit/receive FIFO
Figure 10-2 shows the SCI module block diagram. The SCI port operation is configured and controlled by
the registers listed in Section 10.14 of this chapter.
Figure 10-2. Serial Communications Interface (SCI) Module Block Diagram
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