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SPI Registers
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SPRUI07–March 2020
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Serial Peripheral Interface (SPI)
9.5.2 SPI_REGS Registers
Table 9-5 lists the SPI_REGS registers. All register offset addresses not listed in Table 9-5 should be
considered as reserved locations and the register contents should not be modified.
Table 9-5. SPI_REGS Registers
Offset Acronym Register Name Write Protection Section
0h SPICCR SPI Configuration Control Register Go
1h SPICTL SPI Operation Control Register Go
2h SPISTS SPI Status Register Go
4h SPIBRR SPI Baud Rate Register Go
6h SPIRXEMU SPI Emulation Buffer Register Go
7h SPIRXBUF SPI Serial Input Buffer Register Go
8h SPITXBUF SPI Serial Output Buffer Register Go
9h SPIDAT SPI Serial Data Register Go
Ah SPIFFTX SPI FIFO Transmit Register Go
Bh SPIFFRX SPI FIFO Receive Register Go
Ch SPIFFCT SPI FIFO Control Register Go
Fh SPIPRI SPI Priority Control Register Go
Complex bit access types are encoded to fit into small table cells. Table 9-6 shows the codes that are
used for access types in this section.
Table 9-6. SPI_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
RC R
C
Read
to Clear
Write Type
W W Write
W1C W
1C
Write
1 to clear
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
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