www.ti.com
Receiver Configuration
701
SPRUI07–March 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
12.8.4 Digital Loopback Mode
The DLB bit determines whether the digital loopback mode is on. DLB is described in Table 12-20.
Table 12-20. Register Bit Used to Enable/Disable the Digital Loopback Mode
Register Bit Name Function Type
Reset
Value
SPCR1 15 DLB Digital loopback mode R/W 0
DLB = 0 Digital loopback mode is disabled.
DLB = 1 Digital loopback mode is enabled.
12.8.4.1 Digital Loopback Mode
In the digital loopback mode, the receive signals are connected internally through multiplexers to the
corresponding transmit signals, as shown in Table 12-21. This mode allows testing of serial port code with
a single DSP device; the McBSP receives the data it transmits.
Table 12-21. Receive Signals Connected to Transmit Signals in Digital Loopback Mode
This Receive Signal
Is Fed Internally by
This Transmit Signal
MDR (receive data) MDX (transmit data)
MFSR (receive frame synchronization) MFSX (transmit frame synchronization)
MCLKR (receive clock) MCLKX (transmit clock)
12.8.5 Clock Stop Mode
The CLKSTP bits determine whether the clock stop mode is on. CLKSTP is described in Table 12-22.
Table 12-22. Register Bits Used to Enable/Disable the Clock Stop Mode
Register Bit Name Function Type
Reset
Value
SPCR1 12-11 CLKSTP Clock stop mode R/W 00
CLKSTP = 0Xb Clock stop mode disabled; normal clocking for
non-SPI mode
CLKSTP = 10b Clock stop mode enabled, without clock delay
CLKSTP = 11b Clock stop mode enabled, with clock delay
12.8.5.1 Clock Stop Mode
The clock stop mode supports the SPI master-slave protocol. If you do not plan to use the SPI protocol,
you can clear CLKSTP to disable the clock stop mode.
In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each data
transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP = 11b). The
CLKXP bit determines whether the starting edge of the clock on the MCLKX pin is rising or falling. The
CLKRP bit determines whether receive data is sampled on the rising or falling edge of the clock shown on
the MCLKR pin.
Table 12-23 summarizes the impact of CLKSTP, CLKXP, and CLKRP on serial port operation. In the clock
stop mode, the receive clock is tied internally to the transmit clock, and the receive frame-synchronization
signal is tied internally to the transmit frame-synchronization signal.
To Next Page
Loading...
Need help?
General
