eCAP Registers
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SPRUI07–March 2020
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Enhanced Capture (eCAP)
5.8.2.2 CTRPHS Register (Offset = 2h) [reset = 0h]
CTRPHS is shown in Figure 5-19 and described in Table 5-5.
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Counter Phase Offset Value Register
Figure 5-19. CTRPHS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRPHS
R/W-0h
Table 5-5. CTRPHS Register Field Descriptions
Bit Field Type Reset Description
31-0 CTRPHS R/W 0h
Counter phase value register that can be programmed for phase
lag/lead. This register CTRPHS is loaded into TSCTR upon either a
SYNCI event or S/W force via a control bit. Used to achieve phase
control synchronization with respect to other eCAP and EPWM
timebases.
Reset type: SYSRSn
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