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SPRUI07–March 2020
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List of Figures
List of Figures
1-1. Flash Power Mode State Diagram ....................................................................................... 40
1-2. Flash Pipeline............................................................................................................... 42
1-3. Flash Configuration Access Flow Diagram ............................................................................. 43
1-4. Flash Options Register (FOPT) .......................................................................................... 45
1-5. Flash Power Register (FPWR) ........................................................................................... 45
1-6. Flash Status Register (FSTATUS)....................................................................................... 46
1-7. Flash Standby Wait Register (FSTDBYWAIT) ......................................................................... 47
1-8. Flash Standby to Active Wait Counter Register (FACTIVEWAIT) .................................................. 47
1-9. Flash Wait-State Register (FBANKWAIT) .............................................................................. 48
1-10. OTP Wait-State Register (FOTPWAIT) ................................................................................. 49
1-11. CSM Status and Control Register (CSMSCR) ......................................................................... 54
1-12. Password Match Flow (PMF) ............................................................................................ 55
1-13. Clock and Reset Domains ................................................................................................ 59
1-14. Peripheral Clock Control 0 Register (PCLKCR0) ...................................................................... 60
1-15. Peripheral Clock Control 1 Register (PCLKCR1) ..................................................................... 62
1-16. Peripheral Clock Control 3 Register (PCLKCR3) ...................................................................... 64
1-17. High-Speed Peripheral Clock Prescaler (HISPCP) Register ......................................................... 65
1-18. Low-Speed Peripheral Clock Prescaler Register (LOSPCP)......................................................... 65
1-19. OSC and PLL Block........................................................................................................ 66
1-20. Oscillator Fail-Detection Logic Diagram................................................................................. 67
1-21. XCLKOUT Generation..................................................................................................... 69
1-22. PLLCR Change Procedure Flow Chart.................................................................................. 71
1-23. PLLCR Register Layout ................................................................................................... 72
1-24. PLL Status Register (PLLSTS) ........................................................................................... 72
1-25. Low Power Mode Control 0 Register (LPMCR0)....................................................................... 75
1-26. Watchdog Module.......................................................................................................... 76
1-27. System Control and Status Register (SCSR) .......................................................................... 79
1-28. Watchdog Counter Register (WDCNTR)................................................................................ 80
1-29. Watchdog Reset Key Register (WDKEY)............................................................................... 80
1-30. Watchdog Control Register (WDCR) .................................................................................... 80
1-31. CPU Timers ................................................................................................................. 81
1-32. CPU-Timer Interrupt Signals and Output Signal ....................................................................... 82
1-33. TIMERxTIM Register (x = 0, 1, 2)........................................................................................ 83
1-34. TIMERxTIMH Register (x = 0, 1, 2)...................................................................................... 83
1-35. TIMERxPRD Register (x = 0, 1, 2)....................................................................................... 83
1-36. TIMERxPRDH Register (x = 0, 1, 2)..................................................................................... 83
1-37. TIMERxTCR Register (x = 0, 1, 2)....................................................................................... 84
1-38. TIMERxTPR Register (x = 0, 1, 2) ....................................................................................... 85
1-39. TIMERxTPRH Register (x = 0, 1, 2) .................................................................................... 85
1-40. GPIO0 to GPIO27 Multiplexing Diagram................................................................................ 87
1-41. GPIO28 to GPIO31 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 88
1-42. GPIO32, GPIO33 Multiplexing Diagram................................................................................. 89
1-43. GPIO34 to GPIO63 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 90
1-44. GPIO64 to GPIO79 Multiplexing Diagram (Minimal GPIOs Without Qualification)................................ 91
1-45. Input Qualification Using a Sampling Window.......................................................................... 95
1-46. Input Qualifier Clock Cycles .............................................................................................. 98
1-47. GPIO Port A MUX 1 (GPAMUX1) Register ........................................................................... 104
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