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SPRUI07–March 2020
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List of Figures
1-48. GPIO Port A MUX 2 (GPAMUX2) Register ........................................................................... 106
1-49. GPIO Port B MUX 1 (GPBMUX1) Register ........................................................................... 108
1-50. GPIO Port B MUX 2 (GPBMUX2) Register ........................................................................... 110
1-51. GPIO Port C MUX 1 (GPCMUX1) Register ........................................................................... 112
1-52. GPIO Port C MUX 2 (GPCMUX2) Register ........................................................................... 113
1-53. GPIO Port A Qualification Control (GPACTRL) Register ........................................................... 115
1-54. GPIO Port B Qualification Control (GPBCTRL) Register ........................................................... 116
1-55. GPIO Port A Qualification Select 1 (GPAQSEL1) Register ......................................................... 117
1-56. GPIO Port A Qualification Select 2 (GPAQSEL2) Register ......................................................... 117
1-57. GPIO Port B Qualification Select 1 (GPBQSEL1) Register ......................................................... 118
1-58. GPIO Port B Qualification Select 2 (GPBQSEL2) Register ......................................................... 118
1-59. GPIO Port A Direction (GPADIR) Register ........................................................................... 119
1-60. GPIO Port B Direction (GPBDIR) Register ........................................................................... 119
1-61. GPIO Port C Direction (GPCDIR) Register ........................................................................... 120
1-62. GPIO Port A Pullup Disable (GPAPUD) Registers .................................................................. 120
1-63. GPIO Port B Pullup Disable (GPBPUD) Registers .................................................................. 121
1-64. GPIO Port C Pullup Disable (GPCPUD) Registers .................................................................. 121
1-65. GPIO Port A Data (GPADAT) Register ............................................................................... 122
1-66. GPIO Port B Data (GPBDAT) Register ............................................................................... 122
1-67. GPIO Port C Data (GPCDAT) Register ............................................................................... 123
1-68. GPIO Port A Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers ....................... 124
1-69. GPIO Port B Set, Clear and Toggle (GPBSET, GPBCLEAR, GPBTOGGLE) Registers ....................... 125
1-70. GPIO Port C Set, Clear and Toggle (GPCSET, GPCCLEAR, GPCTOGGLE) Registers ...................... 126
1-71. GPIO XINTn, XNMI Interrupt Select (GPIOXINTnSEL, GPIOXNMISEL) Registers ............................. 127
1-72. GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register................................................ 128
1-73. MAPCNF Register (0x702E) ............................................................................................ 130
1-74. Device Configuration (DEVICECNF) Register ........................................................................ 135
1-75. Part ID Register........................................................................................................... 136
1-76. CLASSID Register........................................................................................................ 136
1-77. REVID Register ........................................................................................................... 136
1-78. Overview: Multiplexing of Interrupts Using the PIE Block ........................................................... 139
1-79. Typical PIE/CPU Interrupt Response - INTx.y ........................................................................ 140
1-80. Reset Flow Diagram...................................................................................................... 142
1-81. PIE Interrupt Sources and External Interrupts XINT1/XINT2 ....................................................... 143
1-82. PIE Interrupt Sources and External Interrupts (XINT3 – XINT7) ................................................... 144
1-83. Multiplexed Interrupt Request Flow Diagram ......................................................................... 147
1-84. PIE Control Register (PIECTRL) (Address CE0) ..................................................................... 154
1-85. PIE Interrupt Acknowledge Register (PIEACK) (Address CE1) .................................................... 154
1-86. PIE Interrupt Enable Register (PIEIERx, x = 1 to 12)................................................................ 155
1-87. PIE Interrupt Flag Register (PIEIFRx, x = 1 to 12) ................................................................... 156
1-88. Interrupt Flag Register (IFR) — CPU Register ....................................................................... 157
1-89. Interrupt Enable Register (IER) — CPU Register .................................................................... 159
1-90. Debug Interrupt Enable Register (DBGIER) — CPU Register...................................................... 161
1-91. External Interrupt n Control Register (XINTnCR)..................................................................... 163
1-92. External NMI Interrupt Control Register (XNMICR) — Address 7077h............................................ 163
1-93. External Interrupt 1 Counter (XINT1CTR) (Address 7078h) ........................................................ 164
1-94. External Interrupt 2 Counter (XINT2CTR) (Address 7079h) ........................................................ 165
1-95. External NMI Interrupt Counter (XNMICTR) (Address 707Fh) ..................................................... 165
2-1. Memory Map of On-Chip ROM ......................................................................................... 167
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