I2C Registers
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SPRUI07–March 2020
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Inter-Integrated Circuit Module (I2C)
11.6.2.11 I2CISRC Register (Offset = Ah) [reset = 0h]
I2CISRC is shown in Figure 11-28 and described in Table 11-20.
Return to the Summary Table.
The I2C interrupt source register (I2CISRC) is a 16-bit register used by the CPU to determine which event
generated the I2C interrupt.
Figure 11-28. I2CISRC Register
15 14 13 12 11 10 9 8
RESERVED WRITE_ZEROS
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED INTCODE
R-0h R-0h
Table 11-20. I2CISRC Register Field Descriptions
Bit Field Type Reset Description
15-12 RESERVED R 0h
Reserved
11-8 WRITE_ZEROS R/W 0h
TI internal testing bits
These reserved bit locations should always be written as zeros.
Reset type: SYSRSn
7-3 RESERVED R 0h
Reserved
2-0 INTCODE R 0h
Interrupt code bits.
The binary code in INTCODE indicates the event that generated an
I2C interrupt.
A CPU read will clear this field. If another lower priority interrupt is
pending and enabled, the value corresponding to that interrupt will
then be loaded. Otherwise, the value will stay cleared.
In the case of an arbitration lost, a no-acknowledgment condition
detected, or a stop condition detected, a CPU read will also clear the
associated interrupt flag bit in the I2CSTR register.
Emulator reads will not affect the state of this field or of the status
bits in the I2CSTR register.
Reset type: SYSRSn
0h (R/W) = None
1h (R/W) = Arbitration lost
2h (R/W) = No-acknowledgment condition detected
3h (R/W) = Registers ready to be accessed
4h (R/W) = Receive data ready
5h (R/W) = Transmit data ready
6h (R/W) = Stop condition detected
7h (R/W) = Addressed as slave
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