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McBSP Registers
759
SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
Figure 12-75. Sample Rate Generator 1 Register (SRGR1)
15 8
FWID
R/W-0
7 0
CLKGDV
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-87. Sample Rate Generator 1 Register (SRGR1) Field Descriptions
Bit Field Value Description
15-8 FWID 0-FFh Frame-synchronization pulse width bits for FSG
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization
signal, FSG. For frame-synchronization pulses on FSG, (FWID + 1) is the pulse width in CLKG
cycles. The eight bits of FWID allow a pulse width of 1 to 256 CLKG cycles:
0 ≤ FWID ≤ 255
1 ≤ (FWID + 1) ≤ 256 CLKG cycles
The period between the frame-synchronization pulses on FSG is defined by the FPER bits.
7-0 CLKGDV 0-FFh Divide-down value for CLKG. The sample rate generator can accept an input clock signal and
divide it down according to CLKGDV to produce an output clock signal, CLKG. The frequency
of CLKG is:
CLKG frequency = (Input clock frequency)/ (CLKGDV + 1)
The input clock is selected by the SCLKME and CLKSM bits:
SCLKME CLKSM Input Clock For
Sample Rate Generator
0 0 Reserved
0 1 LSPCLK
1 0 Signal on MCLKR pin
1 1 Signal on MCLKX pin
12.15.7.2 Sample Rate Generator 2 Register (SRGR2)
The sample rate generator 2 register (SRGR2) is shown in Figure 12-76 and described in Table 12-88.
Figure 12-76. Sample Rate Generator 2 Register (SRGR2)
15 14 13 12 11 8
GSYNC Reserved CLKSM FSGM FPER
R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
7 0
FPER
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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