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ADC Registers
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SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
7.4 ADC Registers
Table 7-9 lists the memory-mapped registers for the ADC. All register offset addresses not listed in
Table 7-9 should be considered as reserved locations and the register contents should not be modified.
The starting address is 7100h.
(1)
The ADC result registers are dual mapped in the device. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait states and left
justified. Locations in Peripheral Frame 0 space (0x0B00-0x0B0F) are 0 wait states and right justified. During high speed/continuous
conversion use of the ADC, use the 0 wait state locations to avoid missing ADC conversions.
Table 7-9. ADC Registers
Offset Offset
(1)
Acronym Register Name Section
0h ADCTRL1 ADC Control Register 1 Section 7.4.1
1h ADCTRL2 ADC Control Register 2 Section 7.4.2
2h ADCMAXCONV ADC Maximum Conversion Channels Register Section 7.4.3
3h ADCCHSELSEQ1 ADC Channel Select Sequencing Control Register
1
Section 7.4.4
4h ADCCHSELSEQ2 ADC Channel Select Sequencing Control Register
2
Section 7.4.5
5h ADCCHSELSEQ3 ADC Channel Select Sequencing Control Register
3
Section 7.4.6
6h ADCCHSELSEQ4 ADC Channel Select Sequencing Control Register
4
Section 7.4.7
7h ADCASEQSR ADC Auto-Sequence Status Register Section 7.4.8
8h to 17h 0h to 9h ADCRESULT_0 to ADCRESULT_15 ADC Conversion Result Register N Section 7.4.9
18h ADCTRL3 ADC Control Register 3 Section 7.4.10
19h ADCST ADC Status Register Section 7.4.11
1Ch ADCREFSEL ADC Reference Select Register Section 7.4.12
1Dh ADCOFFTRIM ADC Offset Trim Register Section 7.4.13
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