Register Descriptions
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SPRUI07–March 2020
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Direct Memory Access (DMA) Module
8.9.10 SRC_BURST_STEP Register (Offset = 1024h + [i * E3h]) [reset = 0h]
SRC_BURST_STEP is shown in Figure 8-17 and described in Table 8-13.
Figure 8-17. SRC_BURST_STEP Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRCBURSTSTEP
R/W-0h
Table 8-13. SRC_BURST_STEP Register Field Descriptions
Bit Field Type Reset Description
15-0 SRCBURSTSTEP R/W 0h These bits specify the source address post-increment/decrement
step size while processing a burst of data:
Only values from -4096 to 4095 are valid.
0000h = No address change
0001h = Add 1 to address
0002h = Add 2 to address
0FFFh = Add 4095 to address
F000h = Sub 4096 from address
FFFEh = Sub 2 from address
FFFFh = Sub 1 from address
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