SPI Registers
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SPRUI07–March 2020
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Serial Peripheral Interface (SPI)
9.5.2.2 SPICTL Register (Offset = 1h) [reset = 0h]
SPICTL is shown in Figure 9-9 and described in Table 9-8.
Return to the Summary Table.
SPICTL controls data transmission, the SPI's ability to generate interrupts, the SPICLK phase, and the
operational mode (slave or master).
Figure 9-9. SPICTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED OVERRUNINT
ENA
CLK_PHASE MASTER_SLA
VE
TALK SPIINTENA
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 9-8. SPICTL Register Field Descriptions
Bit Field Type Reset Description
15-5 RESERVED R 0h
Reserved
4 OVERRUNINTENA R/W 0h
Overrun Interrupt Enable
Overrun Interrupt Enable. Setting this bit causes an interrupt to be
generated when the RECEIVER OVERRUN Flag bit (SPISTS.7) is
set by hardware. Interrupts generated by the RECEIVER OVERRUN
Flag bit and the SPI INT FLAG bit (SPISTS.6) share the same
interrupt vector.
Reset type: SYSRSn
0h (R/W) = Disable RECEIVER OVERRUN interrupts.
1h (R/W) = Enable RECEIVER_OVERRUN interrupts.
3 CLK_PHASE R/W 0h
SPI Clock Phase Select
This bit controls the phase of the SPICLK signal. CLOCK PHASE
and CLOCK POLARITY (SPICCR.6) make four different clocking
schemes possible (see clocking figures in SPI chapter). When
operating with CLOCK PHASE high, the SPI (master or slave)
makes the first bit of data available after SPIDAT is written and
before the first edge of the SPICLK signal, regardless of which SPI
mode is being used.
Reset type: SYSRSn
0h (R/W) = Normal SPI clocking scheme, depending on the
CLOCK POLARITY bit (SPICCR.6).
1h (R/W) = SPICLK signal delayed by one half-cycle. Polarity
determined by the CLOCK POLARITY bit.
2 MASTER_SLAVE R/W 0h
SPI Network Mode Control
This bit determines whether the SPI is a network master or slave.
SLAVE During reset initialization, the SPI is automatically configured
as a network slave.
Reset type: SYSRSn
0h (R/W) = SPI is configured as a slave.
1h (R/W) = SPI is configured as a master.
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