Texas Instruments TMS320 2833 Series User Manual

GPADAT
(latch)
GPACLEAR,
GPATOGGLE
GPAQSEL 1/2
Qual
GPAMUX 1/2
SYSCLKOUT
High
impedance
output
control
GPIO0
to
GPIO27
Pins
PU
XRS
Sync
Lowpower
modesblock
GPIOx.async
GPADIR
(latch)
01
11
01
GPACTRL
2
2
10
Peripheral1input
N/C
(defaultonreset)
(defaultonreset)
GPIOx_OUT
GPIOx_DIR
GPAPUD
0 = enablePU
1 = disablePU
(disabledafterreset)
async
(asyncdisable
whenlow)
11
10
Peripheral2input
Peripheral3input
Peripheral1output
GPASET,
(default
onreset)
3samples
6samples
00
00
XRS
(defaultonreset)
01
11
10
00
01
11
10
00
0=input,1=output
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
External
interrupt
MUX
PIE
GPADAT (read)
GPIOLPMSEL
LPMCR0
Peripheral2output
Peripheral3output
Peripheral1outputenable
Peripheral2outputenable
Peripheral3outputenable
www.ti.com General-Purpose Input/Output (GPIO)
87
SPRUI07–March 2020
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System Control and Interrupts
Figure 1-40. GPIO0 to GPIO27 Multiplexing Diagram
A The shaded area is disabled in the above GPIOs when the GPIOINENCLK bit is cleared to 0 in the PCLKCR3 register
and the respective pin is configured as an output. This is to reduce power consumption when a pin is configured as
an output. Clearing the GPIOINCLK bit will reset the sync and qualification logic so no residual value is left.
B GPxDAT latch/read are accessed at the same memory location.

Texas Instruments TMS320 2833 Series Specifications

General

Brand	Texas Instruments
Model	TMS320 2833 Series
Category	Controller
Language	English