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Configuring Lead, Active, and Trail Wait States
845
SPRUI07–March 2020
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External Interface (XINTF)
14.4 Configuring Lead, Active, and Trail Wait States
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold
times for both read and write accesses. The timing parameters can be configured individually for each
XINTF zone in the XTIMING registers. Each zone can also be configured to either ignore the XREADY
signal or sample it. This allows for optimal efficiency of the XINTF based on the memory or peripheral
being accessed.
Table 14-3 shows the relationship between the parameters that can be configured in the XTIMING
registers and the duration of the pulse in terms of XTIMCLK cycles, t
c(XTIM)
.
(1)
t
c(xtim)
- Cycle time, XTIMCLK
(2)
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY= 0) then WS = 0.
Table 14-3. Pulse Duration in Terms of XTIMCLK Cycles
Description
Duration (ns)
(1) (2)
X2TIMING = 0 X2TIMING = 1
LR Lead period, read access XRDLEAD x t
c(xtim)
(XRDLEADx2) x t
c(xtim)
AR Active period, read access (XRDACTIVE+WS+1) x t
c(xtim)
(XRDACTIVEx2+WS+1) x t
c(xtim)
TR Trail period, read access XRDTRAIL x t
c(xtim)
(XRDTRAILx2) x t
c(xtim)
LW Lead period, write access XWRLEAD x t
c(xtim)
(XWRLEADx2) x t
c(xtim)
AW Active period, write access (XWRACTIVE+WS+1) x t
c(xtim)
(XWRACTIVEx2+WS+1) x t
c(xtim)
TW Trail period, write access XWRTRAIL x t
c(xtim)
(XWRTRAILx2) x t
c(xtim)
NOTE: Minimum wait-state configurations must be used for each zone’s XTIMING register. These
wait-state requirements are in addition to any timing requirements as specified by the device
to which it is interfaced. For information on requirements for a particular device, see the data
sheet for that device.
No internal device hardware is included to detect illegal settings.
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