External DMA Support (XHOLD, XHOLDA)
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External Interface (XINTF)
14.3 External DMA Support (XHOLD, XHOLDA)
The XINTF supports direct memory access (DMA) to its local (off-chip) program and data spaces. This is
accomplished with the XHOLD signal input and XHOLDA output. When XHOLD is asserted (low active) a
request to the external interface is generated to hold all outputs from the external interface a high
impedance state. Upon completion of all outstanding accesses to the external interface, XHOLDA is
asserted (low active). XHOLDA signals external devices that the external interface has its outputs in high-
impedance state and that another device can control access to external memory or peripherals.
The HOLD Mode bit in XINTCNF2 register enables the automatic generation of a XHOLDA signal and
granting access of the external bus, when a valid XHOLD signal is detected. While in HOLD mode, the
CPU can continue to execute code from on-chip memory attached to the memory bus. If an attempt is
made to access the external interface while XHOLDA is low, a not ready condition is generated, halting
the processor. Status bits in the XINTCNF2 register will indicate the state of the XHOLD and XHOLDA
signals.
If XHOLD is active, and the CPU attempts a write to the XINTF, the write is not buffered and the CPU will
stall. The write buffer is disabled.
The HOLD mode bit in XINTCNF2 register bit will take precedence over the XHOLD input signal. Thus
enabling customer code to determine when or not a XHOLD request is to be honored.
The XHOLD input signal is synchronized at the input to the XINTF before any actions are taken.
Synchronization is with respect to XTIMCLK.
The HOLDS bit in XINTCNF2 register reflects the current synchronized state of the XHOLD input.
On reset, the HOLD mode bit is enabled, allowing for bootload of external memory using an XHOLD
request. If XHOLD signal is active low during reset, the XHOLDA signal is driven low as per normal
operation.
During power up, any undefined values in the XHOLD synchronizing latches are ignored and would
eventually be flushed out when the clock stabilizes. Hence, synchronizing latches do not need to be reset.
If an XHOLD active low signal is detected, the XHOLDA signal is only driven low after all pending XINTF
cycles are completed. Any pending CPU cycles are blocked and the CPU is held in a not-ready state if
they are targeted for the XINTF.
Definitions:
Pending XINTF Cycle— Any cycle that is currently in the XINTF FIFO queue.
Pending CPU Cycle— Any cycle that is not in the FIFO queue but is active on the core memory bus.
The XHOLD signal should not be removed until the XHOLDA signal becomes active. Unpredictable results
will occur if this rule should be violated.
The state of the XINTF external signals is as follows in HOLD mode:
Signal HOLD Granted Mode
XA(19:1 ) High-impedance
XD(31:0) High-impedance
XA0/ XWE1 High-impedance
XRD, XWE0, XR/W High-impedance
XZCS0 High-impedance
XZCS6 High-impedance
XZCS7 High-impedance
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