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eCAN Configuration
797
SPRUI07–March 2020
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Controller Area Network (CAN)
13.7.4.3 Interrupt Handling
The CPU is interrupted by asserting one of the two interrupt lines. After handling the interrupt, which
should generally also clear the interrupt source, the interrupt flag must be cleared by the CPU. To do this,
the interrupt flag must be cleared in the CANGIF0 or CANGIF1 register. This is generally done by writing a
1 to the interrupt flag. There are some exceptions to this as stated in Table 13-8. This also releases the
interrupt line if no other interrupt is pending.
(1)
Key to interpreting the table above:
1) Interrupt flag: This is the name of the interrupt flag bit as applicable to CANGIF0/CANGIF1 registers.
2) Interrupt condition: This column illustrates the conditions that cause the interrupt to be asserted.
3) GIF0/GIF1 determination: Interrupt flag bits can be set in either CANGIF0 or CANGIF1 registers. This is determined by either
the GIL bit in CANGIM register or MILn bit in the CANMIL register, depending on the interrupt under consideration. This column
illustrates whether a particular interrupt is dependant on GIL bit or MILn bit.
4) Clearing mechanism: This column explains how a flag bit can be cleared. Some bits are cleared by writing a 1 to it. Other bits
are cleared by manipulating some other bit in the CAN control register.
Table 13-8. eCAN Interrupt Assertion/Clearing
(1)
Interrupt Flag
GIF0/GIF1
Determination
Interrupt Condition Clearing Mechanism
WLIFn One or both error counters are >= 96 GIL bit Cleared by writing a 1 to it
EPIFn CAN module has entered “error passive”
mode
GIL bit Cleared by writing a 1 to it
BOIFn CAN module has entered “bus-off” mode GIL bit Cleared by writing a 1 to it
RMLIFn An overflow condition has occurred in GIL bit Cleared by clearing the set RMPn
one of the receive mailboxes. bit.
WUIFn CAN module has left the local power-down
mode
GIL bit Cleared by writing a 1 to it
WDIFn A write access to a mailbox was denied GIL bit Cleared by writing a 1 to it
AAIFn A transmission request was aborted GIL bit Cleared by clearing the set AAn bit.
GMIFn One of the mailboxes successfully MILn bit Cleared by appropriate handling of
transmitted/received a message the interrupt causing condition. Cleared by
writing a 1 to the ap-propriate bit in CANTA
or CANRMP registers
TCOFn The MSB of the the TSC has changed from
0 to 1
GIL bit Cleared by writing a 1 to it
MTOFn One of the mailboxes did not MILn bit Cleared by clearing the set TOSn
transmit/receive within the specified time
frame.
bit.
13.7.4.3.1 Configuring for Interrupt Handling
To configure for interrupt handling, the mailbox interrupt level register (CANMIL), the mailbox interrupt
mask register (CANMIM), and the global interrupt mask register (CANGIM) need to be configured. The
steps to do this are described below:
1. Write the CANMIL register. This defines whether a successful transmission or reception asserts
interrupt line 0 or 1. For example, CANMIL = 0xFFFFFFFF sets all mailbox interrupts to level 1.
2. Configure the mailbox interrupt mask register (CANMIM) to mask out the mailboxes that should not
cause an interrupt. This register could be set to 0xFFFFFFFF, which enables all mailbox interrupts.
Mailboxes that are not used do not cause any interrupts anyhow.
3. Now configure the CANGIM register. The flags AAIM, WDIM, WUIM, BOIM, EPIM, and WLIM should
always be set (enabling these interrupts). The GIL bit (CANGIM.2) can be cleared to have the global
interrupts on another level than the mailbox interrupts. Both the I1EN (CANGIM.1) and I0EN
(CANGIM.0) flags should be set to enable both interrupt lines. The flag RMLIM (CANGIM.11) can also
be set depending on the load of the CPU.
This configuration puts all mailbox interrupts on line 1 and all system interrupts on line 0. Thus, the CPU
can handle all system interrupts (which are always serious) with high priority, and the mailbox interrupts
(on the other line) with a lower priority. All messages with a high priority can also be directed to the
interrupt line 0.
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