eCAN Configuration
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SPRUI07–March 2020
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Controller Area Network (CAN)
13.7.4.3.2 Handling Mailbox Interrupts
There are three interrupt flags for mailbox interrupts. These are listed below:
GMIF0/GMIF1: One of the objects has received or transmitted a message. The number of the mailbox is
in MIV0/MIV1(GIF0.4-0/GIF1.4-0). The normal handling routine is as follows:
1. Do a half-word read on the GIF register that caused the interrupt. If the value is negative, a mailbox
caused the interrupt. Otherwise, check the AAIF0/AAIF1 (GIF0.14/GIF1.14) bit (abort-acknowledge
interrupt flag) or the RMLIF0/RMLIF1 (GIF0.11/GIF1.11) bit (receive-message-lost interrupt flag).
Otherwise, a system interrupt has occurred. In this case, each of the system-interrupt flags must be
checked.
2. If the RMLIF (GIF0.11) flag caused the interrupt, the message in one of the mailboxes has been
overwritten by a new one. This should not happen in normal operation. The CPU needs to clear that
flag by writing a 1 to it. The CPU must check the receive-message-lost register (RML) to find out which
mailbox caused that interrupt. Depending on the application, the CPU has to decide what to do next.
This interrupt comes together with an GMIF0/GMIF1 interrupt.
3. If the AAIF (GIF.14) flag caused the interrupt, a send transmission operation was aborted by the CPU.
The CPU should check the abort acknowledge register (AA.31-0) to find out which mailbox caused the
interrupt and send that message again if requested. The flag must be cleared by writing a 1 to it.
4. If the GMIF0/GMIF1 (GIF0.15/GIF1.15) flag caused the interrupt, the mailbox number that caused the
interrupt can be read from the MIV0/MIV1 (GIF0.4-0/GIF1.4-0) field. This vector can be used to jump to
a location where that mailbox is handled. If it is a receive mailbox, the CPU should read the data as
described above and clear the RMP.31-0 flag by writing a 1 to it. If it is a send mailbox, no further
action is required, unless the CPU needs to send more data. In this case, the normal send procedure
as described above is necessary. The CPU needs to clear the transmit acknowledge bit (TA.31-0) by
writing a 1 to it.
13.7.4.3.3 Interrupt Handling Sequence
In order for the CPU core to recognize and service CAN interrupts, the following must be done in any CAN
ISR:
1. The flag bit in the CANGIF0/CANGIF1 register which caused the interrupt in the first place must be
cleared. There are two kinds of bits in these registers:
a. the very same bit that needs to be cleared. The following bits fall under this category: TCOFn,
WDIFn, WUIFn, BOIFn, EPIFn, WLIFn
b. The second group of bits are cleared by writing to the corresponding bits in the associated
registers. The following bits fall under this category: MTOFn, GMIFn, AAIFn, RMLIFn
i. The MTOFn bit is cleared by clearing the corresponding bit in the TOS register. For example, if
mailbox 27 caused a time-out condition due to which the MTOFn bit was set, the ISR (after
taking appropriate actions for the timeout condition) needs to clear the TOS27 bit in order to
clear the MTOFn bit.
ii. The GMIFn bit is cleared by clearing the appropriate bit in TA or RMP register. For example, if
mailbox 19 has been configured as a transmit mailbox and has completed a transmission,
TA19 is set, which in turn sets GMIFn. The ISR (after taking appropriate actions) needs to
clear the TA19 bit in order to clear the GMIFn bit. If mailbox 8 has been configured as a
receive mailbox and has completed a reception, RMP8 is set, which in turn sets GMIFn. The
ISR (after taking appropriate actions) needs to clear the RMP8 bit in order to clear the GMIFn
bit.
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