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SPI Registers
571
SPRUI07–March 2020
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Serial Peripheral Interface (SPI)
9.5.2.5 SPIRXEMU Register (Offset = 6h) [reset = 0h]
SPIRXEMU is shown in Figure 9-12 and described in Table 9-11.
Return to the Summary Table.
SPIRXEMU contains the received data. Reading SPIRXEMU does not clear the SPI INT FLAG bit of
SPISTS. This is not a real register but a dummy address from which the contents of SPIRXBUF can be
read by the emulator without clearing the SPI INT FLAG.
Figure 9-12. SPIRXEMU Register
15 14 13 12 11 10 9 8
ERXBn
R-0h
7 6 5 4 3 2 1 0
ERXBn
R-0h
Table 9-11. SPIRXEMU Register Field Descriptions
Bit Field Type Reset Description
15-0 ERXBn R 0h
Emulation Buffer Received Data
SPIRXEMU functions almost identically to SPIRXBUF, except that
reading SPIRXEMU does not clear the SPI INT FLAG bit
(SPISTS.6). Once the SPIDAT has received the complete character,
the character is transferred to SPIRXEMU and SPIRXBUF, where it
can be read. At the same time, SPI INT FLAG is set.
This mirror register was created to support emulation. Reading
SPIRXBUF clears the SPI INT FLAG bit (SPISTS.6). In the normal
operation of the emulator, the control registers are read to
continually update the contents of these registers on the display
screen. SPIRXEMU was created so that the emulator can read this
register and properly update the contents on the display screen.
Reading SPIRXEMU does not clear the SPI INT FLAG bit, but
reading SPIRXBUF clears this flag. In other words, SPIRXEMU
enables the emulator to emulate the true operation of the SPI more
accurately.
It is recommended that you view SPIRXEMU in the normal emulator
run mode.
Reset type: SYSRSn
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