ADC Interface
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SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
There is a sync signal provided automatically by the ADC to the DMA for a sequencer 1 conversion when
both SEQ_OVRD and CONT_RUN bits are set. The sync pulse will be generated by the ADC after the
first MAXCONV limit is reached for each pass through the sequencer. When the sequencer 1 is in this
configuration it is possible that the DMA could become misaligned to the currently populated result
registers, depending on the loading of the other DMA channels. If a misalignment occurs, the DMA can
use the sync signal to detect and flag a sync error event.
For more information on how the sync signal is used locally in the DMA, please see the TMS320x2833x,
2823x Direct Memory Access (DMA) Module Reference Guide.
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