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11
SPRUI07–March 2020
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Contents
13.9 Message Data Registers (CANMDL, CANMDH) ..................................................................... 831
13.10 Acceptance Filter ......................................................................................................... 832
13.10.1 Local-Acceptance Masks (CANLAM)....................................................................... 832
14 External Interface (XINTF).................................................................................................. 834
14.1 Functional Description.................................................................................................... 835
14.1.1 Differences from the TMS320x281x XINTF ................................................................. 835
14.1.2 Differences from the TMS320x2834x XINTF ............................................................... 836
14.1.3 Accessing XINTF Zones ....................................................................................... 836
14.1.4 Write-Followed-by-Read Pipeline Protection................................................................ 837
14.2 XINTF Configuration Overview.......................................................................................... 838
14.2.1 Procedure to Change the XINTF Configuration and Timing Registers .................................. 838
14.2.2 XINTF Clocking ................................................................................................. 839
14.2.3 Write Buffer...................................................................................................... 840
14.2.4 XINTF Access Lead/Active/Trail Wait-State Timing Per Zone............................................ 840
14.2.5 XREADY Sampling For Each Zone .......................................................................... 841
14.2.6 Bank Switching.................................................................................................. 841
14.2.7 Zone Data Bus Width .......................................................................................... 842
14.3 External DMA Support (XHOLD, XHOLDA)........................................................................... 844
14.4 Configuring Lead, Active, and Trail Wait States ...................................................................... 845
14.4.1 USEREADY = 0................................................................................................. 846
14.4.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................... 846
14.4.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1).............................................. 847
14.5 Configuring XBANK Cycles.............................................................................................. 850
14.6 XINTF Registers .......................................................................................................... 851
14.6.1 XRESET Register (Offset = 83Dh) [reset = 0h]............................................................. 852
14.6.2 XTIMING0 Register (Offset = B20h) [reset = 41D2A5h]................................................... 853
14.6.3 XTIMING6 Register (Offset = B2Ch) [reset = 41D2A5h] .................................................. 855
14.6.4 XTIMING7 Register (Offset = B2Eh) [reset = 41D2A5h] .................................................. 857
14.6.5 XBANK Register (Offset = B38h) [reset = 9h] .............................................................. 861
14.6.6 XREVISION Register (Offset = B3Ah) [reset = X].......................................................... 862
14.7 Signal Descriptions ....................................................................................................... 863
14.8 Waveforms................................................................................................................. 864
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