MOV
TBIT
@REG1,AL
@REG2,#BIT_X
Read
Write
XINTF Configuration Overview
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SPRUI07–March 2020
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External Interface (XINTF)
The 28x CPU automatically protects writes followed by reads to the same memory location. The protection
mechanism described above is for cases where the address is not the same, but within a given region of
protected memory. In this case, the order of execution is preserved by the CPU automatically inserting
enough NOP cycles for the write to complete before the read occurs.
This execution ordering becomes a concern only when peripherals are mapped to the XINTF. A write to
one register may update status bits in another register. In this case, the write to the first register must
finish before the read to the second register takes place. If the write and read operations are performed in
the natural pipeline order, the wrong status may be read since the write would happen after the read. This
reversal is not a concern when memory is mapped to the XINTF. Thus, Zone 0 would not typically be used
to access memory but instead would be used only to access external peripherals.
If other zones are used to access peripherals that require write-followed-by-read instruction order to be
preserved the following solutions can be used:
• Add up to 3 NOP assembly instructions between a write and read instructions. Fewer than three can
be used if the code is analyzed and it is found that the pipeline stalls for other reasons.
• Move other instructions before the read to make sure that the write and read are at least three CPU
cycles apart.
• Use the -mv compiler option to automatically insert NOP assembly instructions between write and read
accesses. This option should be used with caution because this out-of-order execution is a concern
only when accessing peripherals mapped to XINTF and not normal memory accesses.
14.2 XINTF Configuration Overview
This section is an overview of the XINTF parameters that can be configured to fit particular system
requirements. The exact configuration used depends on the operating frequency of the 28x, switching
characteristics of the XINTF, and the timing requirements of the external devices. Detailed information on
each of these parameters is given in the following sections.
Because a change to the XINTF configuration parameters will cause a change to the access timing, code
that configures these parameters should not execute from the XINTF itself.
14.2.1 Procedure to Change the XINTF Configuration and Timing Registers
During an XINTF configuration or timing change no accesses to the XINTF can be in progress. This
includes instructions still in the CPU pipeline, write accesses in the XINTF write buffer, data reads or
writes, instruction pre-fetch operations and DMA accesses. To be sure that no access takes place during
the configuration follow these steps:
1. Make sure that the DMA is not accessing the XINTF.
2. Follow the procedure shown in Figure 14-2 to safely modify the XTIMING0/6/7, XBANK, or XINTCNF2
registers.
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