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Configuring Lead, Active, and Trail Wait States
847
SPRUI07–March 2020
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External Interface (XINTF)
14.4.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in asynchronous mode (USEREADY = 1, READYMODE = 1), then the
following requirements must be met:
1 Lead: LR ≥ × t
c(XTIM)
LW ≥ t
c(XTIM)
2 Active: AR ≥ 2 × t
c(XTIM)
AW ≥ 2 × t
c(XTIM)
3 Lead + Active: LR + AR ≥ 4 × t
c(XTIM)
LW + AW ≥ 4 × t
c(XTIM)
These requirements result in the following three possible XTIMING register configurations:
NOTE: Restrictions do not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 1 ≥ 2 0 ≥ 1 ≥ 2 0 0, 1
or
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 2 ≥ 1 0 ≥ 2 ≥ 1 0 0, 1
Examples of valid and invalid timings when using asynchronous XREADY:
(1)
No hardware to detect illegal XTIMING configurations
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
Invalid
(1)
0 0 0 0 0 0 0, 1
Invalid
(1)
1 0 0 1 0 0 0, 1
Invalid
(1)
1 1 0 1 1 0 0
Valid 1 1 0 1 1 0 1
Valid 1 2 0 1 2 0 0, 1
Valid 2 1 0 2 1 0 0, 1
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