Functional Description
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SPRUI07–March 2020
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External Interface (XINTF)
• XINTF Clock Enable:
The XINTF clock (XTIMCLK) is disabled by default to save power. XTIMCLK can be enabled by writing
a 1 to bit 12 of the PCLKCR3 register. PCLKCR3 is documented in the device-specific system control
and interrupts user's guide. For the F2833x devices, it is TMS320F2833x System Control and
Interrupts Reference Guide (literature number SPRUFB0). Turning off XTIMCLK does not turn off
XCLKOUT. There is a separate control to turn off XCLKOUT. On the 281x, XTIMCLK is always
enabled.
• XINTF Pin MUXing:
Many of the XINTF pins are MUXed with general purpose I/O. The GPIO mux registers must be
configured for XINTF operation before using the XINTF. On the 281x, the XINTF has dedicated pins.
• Number of Zones and Chip Select Signals:
The number of XINTF zones has been reduced to 3: Zone 0, Zone 6, and Zone 7. Each of these zones
has a dedicated chip select signal. Zone 0 is still read-followed-by write protected as described in
Section 14.1.4. On the 2812 devices, some zone chip-select signals are shared between zones. Zone
0 and Zone 1 share XZCS0AND1, and Zone 6 and Zone 7 share XZCS6AND7.
• Zone 7 Memory Mapping:
Zone 7 is always mapped. On the 281x devices, the MPNMC input signal determines if Zone 7 is
mapped. Zone 6 and 7 do not share any locations. On 281x devices, Zone 7 is mirrored within Zone 6.
• Zone Memory Map Locations:
Zone 0 starts at address 0x4000 and is 4K x 16. On 281x devices, Zone 0 starts at address 0x2000
and is 8K x 16. Zone 6 and 7 are both 1M x 16 and start at 0x100000 and 0x200000, respectively. On
281x devices, these two zones are 512K x 16 and 16K x 16.
• EALLOW protection:
The XINTF registers are now EALLOW protected. On 281x devices, the XINTF registers were not
EALLOW protected.
Refer to the latest data manual for the device for timing information.
14.1.2 Differences from the TMS320x2834x XINTF
The XINTF described in this chapter is functionally very similar to the TMS320x2834x XINTF. The main
differences are:
• XA0 and WE1
For the F2833x/F2823x devices, XA0 and WE1 share a single pin; however, for the C2834x device,
they are separate pins.
• XBANK Cycle Selection
The number of delay cycles must be configured based on the ratio of XTIMCLK and XCLKOUT. Refer
to Section 14.5. C2834x device do not have this requirement.
Refer to the latest data manual for the device for timing information.
14.1.3 Accessing XINTF Zones
An XINTF zone is a region in the 28x memory map that is directly connected to the external interface.
Figure 14-1 shows zone locations. The memory or peripheral attached to a zone can be accessed directly
with the CPU or Code Composer Studio.
Each XINTF zone can be individually configured with unique read and write access timing and each has
an associated zone chip-select signal. This chip-select signal is pulled low so that an access to that zone
is currently taking place. On 2833x, 2823x devices , all zone chip select signals are independent.
The external address bus, XA, is 20 bits wide and is shared by all of the zones. What external addresses
are generated depends on which zones are being accessed, as follow:
• Zone 0 uses external addresses 0xXX000 - 0xXXFFF. That is, an access to the first location in Zone 0
will issue external addresses 0xXX000 along with chip select 0 (XZCS0). An access to the last location
in the zone will issue address 0xXXFFF with XZCS0. If the upper address lines, indicated by 'XX', are
configured for XINTF functionality, they will be driven but the value is undefined.
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