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XINTF Configuration Overview
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SPRUI07–March 2020
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External Interface (XINTF)
The total active period for any access that does not sample XREADY is 1 XTIMCLK cycle plus the number
wait states specified in the corresponding XTIMING register. By default, the active wait states are set to
the 14 XTIMCLK cycles for both read and write accesses.
The trail period serves as a hold time in which the chip-select signal remains low but the read and write
strobes are brought back high. The total trail period, in XTIMCLK cycles can be configured in the zone’s
XTIMING register. By default the trail period is set to the maximum six XTIMCLK cycles for both read and
write accesses.
Based on system requirements, the lead, active and trail wait state values can be configured to best fit the
devices connected to a particular XINTF zone. The following should be considered when selecting the
timing parameters:
• Minimum wait state requirements as described in Section 14.4
• The timing characteristics of the XINTF, as described in the device data manual
• The timing requirements of the external device
• Any additional delays between the 28x device and the external device
14.2.5 XREADY Sampling For Each Zone
By sampling XREADY, the external device can extend the active portion of the access. All of the XINTF
zones on a device share the same XREADY input signal but each XINTF zone can individually be
configured to either sample or ignore the XREADY signal. In addition, the sampling can be specified as
synchronous or asynchronous for each zone.
• Synchronous sampling
If XREADY is sampled synchronously, then the XREADY signal must meet set-up and hold timing
relative to one XTIMCLK edge before the end of the active period. That is, XREADY will be sampled
one XTIMCLK cycle before the total lead + active cycles specified for the access.
• Asynchronous sampling
If XREADY is sampled asynchronously, then the XREADY signal must meet set-up and hold timing
relative to three XTIMCLK cycles before the end of the active period. That is, XREADY will be sampled
three XTIMCLK cycles before the total lead + active cycles specified for the access.
In both the synchronous and asynchronous case if the XREADY sample is found to be low, the active
portion of the cycle is extended by one XTIMCLK cycle and XREADY is sampled again during the next
XTIMCLK cycle. This pattern continues until XREADY is sampled high at which time the access will
complete normally.
If a zone is configured to sample XREADY, then it is done so for both read and write accesses to that
zone. By default each XINTF zone is configured to sample XREADY in the asynchronous mode. When
using the XREADY signal, the minimum XINTF wait state requirements must be satisfied as described in
Section 14.4. The minimum requirements are different when sampling XREADY in the synchronous mode
vs the asynchronous mode, depending on the following:
• The timing characteristics of the XINTF, as described in the device data sheet.
• The timing requirements of the external device.
• Any additional delays between the 28x device and the external device.
14.2.6 Bank Switching
When jumping from one XINTF zone to another XINTF zone, a slow device may require extra cycles in
order to release the bus in time for another device to gain access. Bank switching allows the XINTF to add
extra cycles for any access that crosses into or out of the specified zone. The zone and number of cycles
is configured in the XBANK register. The number of cycles must meet the requirements described in
Section 14.5.
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