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System-Level Integration
551
SPRUI07–March 2020
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Serial Peripheral Interface (SPI)
Special Considerations
The SPISTE signal provides the ability to gate any spurious clock and data pulses when the SPI is in
slave mode. An active SPISTE will not allow the slave to receive data. This prevents the SPI slave from
losing synchronization with the master. It is this reason that TI does not recommend that the SPISTE
always be tied to the active state.
If the SPI slave does ever lose synchronization with the master, toggling SPISWRESET will reset internal
bit counter as well as the various status flags in the module. By resetting the bit counter, the SPI will
interpret the next clock transition as the first bit of a new transmission. The register bit fields which are
reset by SPISWRESET can be found in Section 9.5
Configuring a GPIO to emulate SPISTE
In many systems, a SPI master may be connected to multiple SPI slaves using multiple instances of
SPISTE. Though this SPI module does not natively support multiple SPISTE signals, it is possible to
emulate this behavior in software using GPIOs. In this configuration, the SPI must be configured as the
master. Rather than using the GPIO Mux to select SPISTE, the application would configure pins to be
GPIO outputs, one GPIO per SPI slave. Before transmitting any data, the application would drive the
desired GPIO to the active state. Immediately after the transmission has been completed, the GPIO chip
select would be driven to the inactive state. This process can be repeated for many slaves which share
the SPICLK, SPISIMO, and SPISOMI lines.
9.2.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.
9.2.3 SPI Interrupts
This section includes information on the available interrupts present in the SPI module.
The SPI module contains two interrupt lines: SPIINT/SPIRXINT and SPITXINT. When the SPI is operating
in non-FIFO mode, all available interrupts are routed together to generate the single SPIINT interrupt.
When FIFO mode is used, both SPIRXINT and SPITXINT can be generated.
SPIINT/SPIRXINT
When the SPI is operating in non-FIFO mode, the interrupt generated is called SPIINT. If FIFO
enhancements are enabled, the interrupt is called SPIRXINT. These interrupts share the same interrupt
vector in the Peripheral Interrupt Expansion (PIE) block.
In non-FIFO mode, two conditions can trigger an interrupt: a transmission is complete (INT_FLAG), or
there is overrun in the receiver (OVERRUN_FLAG). Both of these conditions share the same interrupt
vector: SPIINT.
The transmission complete flag (INT_FLAG) indicates that the SPI has completed sending or receiving the
last bit and is ready to be serviced. At the same time this bit is set, the received character is placed in the
receiver buffer (SPIRXBUF). The INT_FLAG will generate an interrupt on the SPIINT vector if the
SPIINTENA bit is set.
The receiver overrun flag (OVERRUN_FLAG) indicates that a transmit or receive operation has completed
before the previous character has been read from the buffer. The OVERRUN_FLAG will generate an
interrupt on the SPIINT vector if the OVERRUNINTENA bit is set and OVERRUN_FLAG was previously
cleared.
In FIFO mode, the SPI can interrupt the CPU upon a match condition between the current receive FIFO
status (RXFFST) and the receive FIFO interrupt level (RXFFIL). If RXFFST is greater than or equal to
RXFFIL, the receive FIFO interrupt flag (RXFFINT) will be set. SPIRXINT will be triggered in the PIE block
if RXFFINT is set and the receive FIFO interrupt is enabled (RXFFIENA = 1).
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