ADC Interface
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SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
7.3.2 Autoconversion Sequencer Principle of Operation
The ADC sequencer consists of two independent 8-state sequencers (SEQ1 and SEQ2) that can also be
cascaded together to form one 16-state sequencer (SEQ). The word "state" represents the number of
autoconversions that can be performed with the sequencer. Block diagrams of the single (16-state,
cascaded) and dual (two 8-state, separated) sequencer modes are shown in Figure 7-8 and Figure 7-9,
respectively.
In both cases, the ADC has the ability to autosequence a series of conversions. This means that each
time the ADC receives a start-of-conversion request, it can perform multiple conversions automatically.
For every conversion, any one of the available 16 input channels can be selected through the analog
MUX. After conversion, the digital value of the selected channel is stored in the appropriate result register
(ADCRESULTn). (The first result is stored in ADCRESULT0, the second result in ADCRESULT1, and so
on). It is also possible to sample the same channel multiple times, allowing the user to perform "over-
sampling", which gives increased resolution over traditional single-sampled conversion results.
NOTE: In the sequential sampling dual-sequencer mode, a pending SOC request from either
sequencer is taken up as soon as the sequence initiated by the currently active sequencer is
finished. For example, assume that the A/D converter is busy catering to SEQ2 when an
SOC request from SEQ1 occurs. The A/D converter will start SEQ1 immediately after
completing the request in progress on SEQ2. If SOC requests are pending from both SEQ1
and SEQ2, the SOC for SEQ1 has priority. For example, assume that the A/D converter is
busy catering to SEQ1. During that process, SOC requests from both SEQ1 and SEQ2 are
made. When SEQ1 completes its active sequence, the SOC request for SEQ1 will be taken
up immediately. The SOC request for SEQ2 will remain pending.
The ADC can also operate in simultaneous sampling mode or sequential sampling mode. For each
conversion (or pair of conversions in simultaneous sampling mode), the current CONVxx bit field defines
the pin (or pair of pins) to be sampled and converted. In sequential sampling mode, all four bits of
CONVxx define the input pin. The MSB defines which sample-and-hold buffer the input pin is associated
with, and the three LSBs define the offset. For example, if CONVxx contains the value 0101b, ADCINA5 is
the selected input pin. If it contains the value 1011b, ADCINB3 is the selected input pin. In simultaneous
sampling mode, the MSB of the CONVxx register is discarded. Each sample and hold buffer samples the
associated pin given by the offset provided in the three LSBs of the CONVxx register. For instance, if the
CONVxx register contains the value 0110b, ADCINA6 is sampled by S/H-A and ADCINB6 is sampled by
S/H-B. If the value is 1001b, ADCINA1 is sampled by S/H-A and ADCINB1 is sampled by S/H-B. The
voltage in S/H-A is converted first, followed by the S/H-B voltage. The result of the S/H-A conversion is
placed in the current ADCRESULTn register (ADCRESULT0 for SEQ1, assuming the sequencer has been
reset). The result of the S/H-B conversion is placed in the next ADCRESULTn register (ADCRESULT1 for
SEQ1, assuming the sequencer has been reset). The result register pointer is then increased by two (to
point to ADCRESULT2 for SEQ1, assuming the sequencer had originally been reset).
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