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SPRUI07–March 2020
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List of Figures
3-56. Timing Waveforms Associated With Phase Control Between 2 Modules......................................... 289
3-57. Control of a 3-Phase Interleaved DC/DC Converter ................................................................. 290
3-58. 3-Phase Interleaved DC/DC Converter Waveforms for ............................................................. 291
3-59. Controlling a Full-H Bridge Stage (F
PWM2
= F
PWM1)
.................................................................... 293
3-60. ZVS Full-H Bridge Waveforms.......................................................................................... 294
3-61. Time-Base Period Register (TBPRD) .................................................................................. 296
3-62. Time-Base Phase Register (TBPHS) .................................................................................. 296
3-63. Time-Base Counter Register (TBCTR) ................................................................................ 296
3-64. Time-Base Control Register (TBCTL).................................................................................. 297
3-65. Time-Base Status Register (TBSTS)................................................................................... 299
3-66. Counter-Compare A Register (CMPA) ................................................................................ 300
3-67. Counter-Compare B Register (CMPB)................................................................................. 301
3-68. Counter-Compare Control Register (CMPCTL)....................................................................... 302
3-69. Compare A High Resolution Register (CMPAHR) ................................................................... 303
3-70. Action-Qualifier Output A Control Register (AQCTLA)............................................................... 304
3-71. Action-Qualifier Output B Control Register (AQCTLB)............................................................... 305
3-72. Action-Qualifier Software Force Register (AQSFRC)................................................................ 306
3-73. Action-Qualifier Continuous Software Force Register (AQCSFRC)................................................ 307
3-74. Dead-Band Generator Control Register (DBCTL).................................................................... 308
3-75. Dead-Band Generator Rising Edge Delay Register (DBRED)...................................................... 309
3-76. Dead-Band Generator Falling Edge Delay Register (DBFED) ..................................................... 310
3-77. PWM-Chopper Control Register (PCCTL)............................................................................. 311
3-78. Trip-Zone Select Register (TZSEL) .................................................................................... 313
3-79. Trip-Zone Control Register (TZCTL) ................................................................................... 315
3-80. Trip-Zone Enable Interrupt Register (TZEINT)........................................................................ 316
3-81. Trip-Zone Flag Register (TZFLG)....................................................................................... 317
3-82. Trip-Zone Clear Register (TZCLR) ..................................................................................... 318
3-83. Trip-Zone Force Register (TZFRC)..................................................................................... 319
3-84. Event-Trigger Selection Register (ETSEL) ............................................................................ 320
3-85. Event-Trigger Prescale Register (ETPS) .............................................................................. 322
3-86. Event-Trigger Flag Register (ETFLG).................................................................................. 323
3-87. Event-Trigger Clear Register (ETCLR) ................................................................................ 324
3-88. Event-Trigger Force Register (ETFRC)................................................................................ 325
4-1. Resolution Calculations for Conventionally Generated PWM....................................................... 327
4-2. Operating Logic Using MEP............................................................................................. 328
4-3. HRPWM Extension Registers and Memory Configuration .......................................................... 329
4-4. HRPWM System Interface............................................................................................... 329
4-5. Required PWM Waveform for a Requested Duty = 40.5% ......................................................... 331
4-6. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ............................... 334
4-7. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ............................... 335
4-8. Simple Buck Controlled Converter Using a Single PWM............................................................ 340
4-9. PWM Waveform Generated for Simple Buck Controlled Converter ............................................... 340
4-10. Simple Reconstruction Filter for a PWM Based DAC................................................................ 343
4-11. PWM Waveform Generated for the PWM DAC Function ........................................................... 343
4-12. HRPWM Configuration Register (HRCNFG).......................................................................... 347
4-13. Counter Compare A High-Resolution Register (CMPAHR) ......................................................... 347
4-14. Time Base Phase High-Resolution Register (TBPHSHR)........................................................... 348
5-1. Multiple eCAP Modules In A C28x System............................................................................ 352
5-2. Capture and APWM Modes of Operation.............................................................................. 353
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