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ePWM Submodules
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SPRUI07–March 2020
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Enhanced Pulse Width Modulator (ePWM) Module
NOTE: All modules shown in the synchronization schemes may not be available on all devices.
Please refer to the datasheet to determine which modules are available on a particular
device.
Each ePWM module can be configured to use or ignore the synchronization input. If the TBCTL[PHSEN]
bit is set, then the time-base counter (TBCTR) of the ePWM module will be automatically loaded with the
phase register (TBPHS) contents when one of the following conditions occur:
• EPWMxSYNCI: Synchronization Input Pulse:
The value of the phase register is loaded into the counter register when an input synchronization pulse
is detected (TBPHS → TBCTR). This operation occurs on the next valid time-base clock (TBCLK)
edge.
The delay from internal master module to slave modules is given by:
– if ( TBCLK = SYSCLKOUT): 2 x SYSCLKOUT
– if ( TBCLK != SYSCLKOUT):1 TBCLK
• Software Forced Synchronization Pulse:
Writing a 1 to the TBCTL[SWFSYNC] control bit invokes a software forced synchronization. This pulse
is ORed with the synchronization input signal, and therefore has the same effect as a pulse on
EPWMxSYNCI.
• This feature enables the ePWM module to be automatically synchronized to the time base of another
ePWM module. Lead or lag phase control can be added to the waveforms generated by different
ePWM modules to synchronize them. In up-down-count mode, the TBCTL[PSHDIR] bit configures the
direction of the time-base counter immediately after a synchronization event. The new direction is
independent of the direction prior to the synchronization event. The PHSDIR bit is ignored in count-up
or count-down modes. See Figure 3-8 through Figure 3-11 for examples.
Clearing the TBCTL[PHSEN] bit configures the ePWM to ignore the synchronization input pulse. The
synchronization pulse can still be allowed to flow-through to the EPWMxSYNCO and be used to
synchronize other ePWM modules. In this way, you can set up a master time-base (for example, ePWM1)
and downstream modules (ePWM2 - ePWMx) may elect to run in synchronization with the master. See
the Application to Power Topologies Section 3.3 for more details on synchronization strategies.
3.2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM
modules on a device. This bit is part of the device's clock enable registers and is described in the specific
device version of the System Control and Interrupts chapter. When TBCLKSYNC = 0, the time-base clock
of all ePWM modules is stopped (default). When TBCLKSYNC = 1, all ePWM time-base clocks are started
with the rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescaler bits in the
TBCTL register of each ePWM module must be set identically. The proper procedure for enabling the
ePWM clocks is as follows:
1. Enable the individual ePWM module clocks. This is described in the specific device version of the
System Control and Interrupts chapter .
2. Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
3. Configure the prescaler values and desired ePWM modes.
4. Set TBCLKSYNC = 1.
3.2.2.5 Time-base Counter Modes and Timing Waveforms
The time-base counter operates in one of four modes:
• Up-count mode which is asymmetrical.
• Down-count mode which is asymmetrical.
• Up-down-count which is symmetrical
• Frozen where the time-base counter is held constant at the current value
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