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Operational Description of HRPWM
333
SPRUI07–March 2020
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High-Resolution Pulse Width Modulator (HRPWM)
NOTE: The MEP scale factor (MEP_ScaleFactor) varies with the system clock and device operating
conditions. TI provides an MEP scale factor optimizing (SFO) software C function, which
uses the built in diagnostics in each HRPWM and returns the best scale factor for a given
operating point.
The scale factor varies slowly over a limited range so the optimizing C function can be run
very slowly in a background loop.
The CMPA and CMPAHR registers are configured in memory so that the 32-bit data
capability of the 28x CPU can write this as a single concatenated value, that is,
[CMPA:CMPAHR].
The mapping scheme has been implemented in both C and assembly, as shown in
Section 4.2.5. The actual implementation takes advantage of the 32-bit CPU architecture of
the 28xx, and is somewhat different from the steps shown in Section 4.2.3.2.
For time critical control loops where every cycle counts, the assembly version is
recommended. This is a cycle optimized function (11 SYSCLKOUT cycles ) that takes a Q15
duty value as input and writes a single [CMPA:CMPAHR] value.
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