Digital Value + 0,
Digital Value + 4096
Input Analog Voltage * ADCLO
3
when input ≤ 0 V
when 0 V < input < 3 V
when input ≥ 3 VDigital Value + 4095,
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Features and Implementation
447
SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
The two 8-channel modules can autosequence a series of conversions; each module has the choice of
selecting any one of the respective eight channels available through an analog MUX. In the cascaded
mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the
conversion is completed, the selected channel value is stored in its respective ADCRESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to
perform oversampling algorithms. This oversampling gives increased resolution over traditional single-
sampled conversion results.
Functions of the ADC module include:
• 12-bit ADC core with built-in dual sample-and-hold (S/H)
• Simultaneous sampling or sequential sampling modes
• Analog input: 0 V to 3 V
• Fast conversion time runs at 25 MHz, ADC clock, or 12.5 MSPS
• 16-channel, multiplexed inputs
• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion
can be programmed to select any 1 of 16 input channels.
• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state
sequencer (that is, two cascaded 8-state sequencers).
• Sixteen result registers (individually addressable) to store conversion values
– The digital value of the input analog voltage is derived by:
NOTE: All fractional values are truncated.
• Multiple triggers as sources for the start-of-conversion (SOC) sequence
– S/W - software immediate start
– ePWM 1-6
– GPIO XINT2
• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
• Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to
synchronize conversions.
• ePWM triggers can operate independently in dual-sequencer mode.
• Sample-and-hold (S/H) acquisition time window has separate prescale control.
NOTE: To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best
extent possible, traces leading to the ADCINxx pins should not run in close proximity to the
digital signal paths. This is to minimize switching noise on the digital lines from getting
coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate
the ADC module power pins from the digital supply. The TMDSCNCD28335 controlCARD
can be used as a reference for the above constraints.
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