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ADC Circuit
451
SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
7.2.2.1 ACQPS Approximation for High Bandwidth Signals
Signals that must be sampled frequently with minimal phase delay (such as feedback sensors used in
control-loop calculations) are high bandwidth signals. These signal paths require a small R
s
C
s
time
constant as seen by the ADCINx pin. An external signal buffer (such as an op-amp) may be used to boost
the sampling bandwidth; such buffers should ideally have a bandwidth that is high enough to fully charge
C
h
within the selected ACPQS S+H window.
7.2.2.1.1 ACQPS Approximation Equations for High Bandwidth Signals
An approximation of the required settling time can be determined using an RC settling model. The time
constant (τ) for the model is given by the equation:
And the number of time constants needed is given by the equation:
So the total S+H time (t
S+H
)should be set to at least:
Finally, t
S+H
is used to determine the minimum value to program into the ACQPS field of the
ADCSOCxCTL registers:
Where the following parameters are provided by the ADC input model:
• n = ADC resolution (in bits)
• R
on
= ADC sampling switch resistance
• C
h
= ADC sampling capacitor
• C
p
= ADC parasitic pin capacitance for the channel
And the following parameters are dependent on the application design:
• settling error = tolerable settling error (in LSBs)
• R
s
= ADC driving circuit source impedance
• C
s
= ADC driving circuit source capacitance on ADC input pin
• f
ADCCLK
= ADC clock frequency
7.2.2.1.2 ACQPS Approximation Example for High Bandwidth Signals
For example, assuming the following parameters:
• n = 12-bits
• settling error =¼ LSB
• R
on
= 1000Ω
• C
h
= 1.6pF
• C
p
= 10pF
• R
s
= 56Ω
• C
s
= 2.2nF
• f
ADCCLK
= 30MHz
The time constant would be calculated as:
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