Introduction
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SPRUI07–March 2020
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Direct Memory Access (DMA) Module
8.1 Introduction
The strength of a digital signal controller (DSC) is not measured purely in processor speed, but in total
system capabilities. As a part of the equation, any time the CPU bandwidth for a given function can be
reduced, the greater the system capabilities. Many times applications spend a significant amount of their
bandwidth moving data, whether it is from off-chip memory to on-chip memory, or from a peripheral such
as an analog-to-digital converter (ADC) to RAM, or even from one peripheral to another. Furthermore,
many times this data comes in a format that is not conducive to the optimum processing powers of the
CPU. The DMA module described in this reference guide has the ability to free up CPU bandwidth and
rearrange the data into a pattern for more streamlined processing.
The DMA module is an event-based machine, meaning it requires a peripheral interrupt trigger to start a
DMA transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the
interrupt trigger source, there is no mechanism within the module itself to start memory transfers
periodically. The interrupt trigger source for each of the six DMA channels can be configured separately
and each channel contains its own independent PIE interrupt to let the CPU know when a DMA transfers
has either started or completed. Five of the six channels are exactly the same, while Channel 1 has one
additional feature: the ability to be configured at a higher priority than the others. At the heart of the DMA
is a state machine and tightly coupled address control logic. It is this address control logic that allows for
rearrangement of the block of data during the transfer as well as the process of ping-ponging data
between buffers. Each of these features, along with others will be discussed in detail in this document.
DMA Overview:
• 6 channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC sequencer 1 and sequencer 2
– Multichannel Buffered Serial Port A and B (McBSP-A, McBSP-B) transmit and receive
– XINT1-7 and XINT13
– CPU Timers
– Software
– ePWM1-6 ADCSOCA and ADSOCB signals
• Data sources/destinations:
– L4-L7 16K x 16 SARAM
– All XINTF zones
– ADC memory bus mapped result registers
– McBSP-A and McBSP-B transmit and receive buffers
– ePWM1-6 / HRPWM1-6 Peripheral Frame 3 mapped registers
• Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit)
• Throughput: 4 cycles/word (5 cycles/word for McBSP reads)
NOTE: The ePWM/HRPWM are not present on all devices and/or revisions. See the TMS320x28xx,
28xxx device Peripheral Reference Guide ( SPRU566) for specifics.
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