Address Pointer and Transfer Control
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SPRUI07–March 2020
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Direct Memory Access (DMA) Module
Three modes are provided to control the way the state machine behaves during the burst loop and the
transfer loop:
One Shot Mode (ONESHOT)— If one shot mode is enabled when an interrupt event trigger occurs, the
DMA will continue transferring data in bursts until TRANSFER_COUNT is zero. If one shot mode is
disabled, then an interrupt event trigger is required for each burst transfer and this will continue until
TRANSFER_COUNT is zero.
NOTE: When ONESHOT mode is enabled, the DMA will continuously transfer bursts of data on the
given channel until the TRANSFER_COUNT value is zero. This could potentially hog the
bandwidth of a peripheral and cause long CPU stalls to occur. To avoid this, you could
configure a CPU timer (or similar) and disable ONESHOT so as to avoid this situation.
High-priority mode and ONESHOT mode may not be used at the same time on channel 1.
Other channels may use ONESHOT mode when channel 1 is in high-priority mode.
Continuous Mode (CONTINUOUS)— If continuous mode is disabled the RUNSTS bit in the CONTROL
register is cleared at the end of the transfer, disabling the DMA channel.
The channel must be re-enabled by setting the RUN bit in the CONTROL register before another
transfer can be started on that channel. If the continuous mode is enabled the RUNSTS bit is not
cleared at the end of the transfer.
Channel Interrupt Mode (CHINTMODE)— This mode bit selects whether the DMA interrupt from the
respective channel is generated at the beginning of a new transfer or at the end of the transfer.
If implementing a ping-pong buffer scheme with continuous mode of operation, then the interrupt
would be generated at the beginning, just after the working registers are copied to the shadow set.
If the DMA does not operate in continuous mode, then the interrupt is typically generated at the end
when the transfer is complete.
All of the above features and modes are shown in Figure 8-5.
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