ADC Sync Feature
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SPRUI07–March 2020
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Direct Memory Access (DMA) Module
The following items are in reference to Figure 8-5.
• The HALT points represent where the channel halts operation when interrupted by a high priority
channel 1 trigger, or when the HALT command is set, or when an emulation halt is issued and the
FREE bit is cleared to 0.
• The ADDR registers are not affected by BEG_ADDR at the start of a transfer. BEG_ADDR only affects
the ADDR registers on a wrap or sync error. Following is what happens to each of the ADDR registers
when a transfer first starts:
– BEG_ADDR_SHADOW remains unchanged.
– ADDR_SHADOW remains unchanged.
– BEG_ADDR = BEG_ADDR_SHADOW
– ADDR = ADDR_SHADOW
• The active registers get updated when a wrap occurs. The shadow registers remain unchanged.
Specifically:
– BEG_ADDR_SHADOW remains unchanged.
– ADDR_SHADOW remains unchanged.
– BEG_ADDR += WRAP_STEP
– ADDR = BEG_ADDR
• The active registers get updated when a sync error occurs. The shadow registers remain unchanged.
Specifically:
– BEG_ADDR_SHADOW remains unchanged.
– ADDR_SHADOW remains unchanged.
– BEG_ADDR remains unchanged.
– ADDR = BEG_ADDR
Probably the easiest way to remember all this is that:
• The shadow registers never change except by software.
• The active registers never change except by hardware, and a shadow register is only copied into its
own active register, never an active register by another name.
8.7 ADC Sync Feature
The DMA provides a hardware method of synchronizing to the ADC Sequencer 1 interrupt (SEQ1INT)
when it is running in continuous conversion mode with the sequencer override function enabled. In this
specific mode, the ADC will be continuously converting a sequence of ADC channels without resetting the
sequencer pointer at the end of each sequence. Since the DMA does not know which ADC RESULT
register the sequencer pointer is pointing to when it receives a trigger, there is a potential for the DMA and
the ADC to be out of step. For this reason, when the ADC is configured in this mode, it provides a
synchronization signal to the DMA each time an event trigger is generated for a sequence starting at the
RESULT0 register. The DMA expects this signal to line up with a wrap procedure or the beginning of a
transfer. If it does not, a re-sync procedure occurs:
1. Reload the WRAP_COUNT register with WRAP_SIZE
2. Load the ADDR.active register with BEG_ADDR.active
3. Set the SYNCERR bit in the CONTROL register
This allows the use of multiple buffers to store the data and for the DMA and the ADC to resynchronize if
necessary. For example, assume four ADC channels are configured to be converted at a time on
sequencer 1. Since the maximum length of sequencer 1 is eight elements, the sequencer will reset itself,
and generate a sync signal every other sequence. Assume the software expects that the first four results
will be placed by the DMA into Buffer A, and the second four into Buffer B. If DMA activity becomes
overburdened and an event trigger is lost, the DMA and the ADC will become unsynchronized. At this
point the DMA will set the SYNCERR bit in the CONTROL register and perform the above re-sync
procedure, bringing the DMA and the ADC back into synchronization.
Alternatively, the sync feature can be configured to work on the source address pointer via the SYNCSEL
bit in the MODE register.
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