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SPI Operation
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SPRUI07–March 2020
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Serial Peripheral Interface (SPI)
9.3.2 Master Mode
In master mode (MASTER_SLAVE = 1), the SPI provides the serial clock on the SPICLK pin for the entire
serial communications network. Data is output on the SPISIMO pin and latched from the SPISOMI pin.
The SPIBRR register determines both the transmit and receive bit transfer rate for the network. SPIBRR
can select 125 different data transfer rates.
Data written to SPIDAT or SPITXBUF initiates data transmission on the SPISIMO pin, MSB (most
significant bit) first. Simultaneously, received data is shifted through the SPISOMI pin into the LSB (least
significant bit) of SPIDAT. When the selected number of bits has been transmitted, the received data is
transferred to the SPIRXBUF (buffered receiver) for the CPU to read. Data is stored right-justified in
SPIRXBUF.
When the specified number of data bits has been shifted through SPIDAT, the following events occur:
• SPIDAT contents are transferred to SPIRXBUF.
• INT_FLAG bit is set to 1.
• If there is valid data in the transmit buffer SPITXBUF, as indicated by the Transmit Buffer Full Flag
(BUFFULL_FLAG), this data is transferred to SPIDAT and is transmitted; otherwise, SPICLK stops
after all bits have been shifted out of SPIDAT.
• If the SPIINTENA bit is set to 1, an interrupt is asserted.
In a typical application, the SPISTE pin serves as a chip-enable pin for a slave SPI device. This pin is
driven low by the master before transmitting data to the slave and is taken high after the transmission is
complete.
9.3.3 Slave Mode
In slave mode (MASTER_SLAVE = 0), data shifts out on the SPISOMI pin and in on the SPISIMO pin.
The SPICLK pin is used as the input for the serial shift clock, which is supplied from the external network
master. The transfer rate is defined by this clock. The SPICLK input frequency should be no greater than
the LSPCLK frequency divided by 4.
Data written to SPIDAT or SPITXBUF is transmitted to the network when appropriate edges of the
SPICLK signal are received from the network master. Data written to the SPITXBUF register will be
transferred to the SPIDAT register when all bits of the character to be transmitted have been shifted out of
SPIDAT. If no character is currently being transmitted when SPITXBUF is written to, the data will be
transferred immediately to SPIDAT. To receive data, the SPI waits for the network master to send the
SPICLK signal and then shifts the data on the SPISIMO pin into SPIDAT. If data is to be transmitted by
the slave simultaneously, and SPITXBUF has not been previously loaded, the data must be written to
SPITXBUF or SPIDAT before the beginning of the SPICLK signal.
When the TALK bit is cleared, data transmission is disabled, and the output line (SPISOMI) is put into the
high-impedance state. If this occurs while a transmission is active, the current character is completely
transmitted even though SPISOMI is forced into the high-impedance state. This ensures that the SPI is
still able to receive incoming data correctly. This TALK bit allows many slave devices to be tied together
on the network, but only one slave at a time is allowed to drive the SPISOMI line.
The SPISTE pin operates as the slave-select pin. An active-low signal on the SPISTE pin allows the slave
SPI to transfer data to the serial data line; an inactive- high signal causes the slave SPI serial shift register
to stop and its serial output pin to be put into the high-impedance state. This allows many slave devices to
be tied together on the network, although only one slave device is selected at a time.
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