Programming Procedure
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SPRUI07–March 2020
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Serial Peripheral Interface (SPI)
9.4 Programming Procedure
This section describes the procedure for configuring the SPI for the various modes of operation.
9.4.1 Initialization Upon Reset
A system reset forces the SPI peripheral into the following default configuration:
• Unit is configured as a slave module (MASTER_SLAVE = 0)
• Transmit capability is disabled (TALK = 0)
• Data is latched at the input on the falling edge of the SPICLK signal
• Character length is assumed to be one bit
• SPI interrupts are disabled
• Data in SPIDAT is reset to 0000h
9.4.2 Configuring the SPI
This section describes the procedure in which to configure the SPI module for operation. To prevent
unwanted and unforeseen events from occurring during or as a result of initialization changes, clear the
SPISWRESET bit before making initialization changes, and then set this bit after initialization is complete.
While the SPI is held in reset (SPISWRESET = 0), configuration may be changed in any order. The
following list shows the SPI configuration procedure in a logical order. However, the SPI registers can be
written with single 16-bit writes, so the order is not required with the exception of SPISWRESET.
To change the SPI configuration:
Step 1. Clear the SPI Software Reset bit (SPISWRESET) to 0 to force the SPI to the reset state.
Step 2. Configure the SPI as desired:
• Select either master or slave mode (MASTER_SLAVE).
• Choose SPICLK polarity and phase (CLKPOLARITY and CLK_PHASE).
• Set the desired baud rate (SPIBRR).
• Set the SPI character length (SPICHAR).
• Clear the SPI Flags (OVERRUN_FLAG, INT_FLAG).
• If using FIFO enhancements:
– Enable the FIFO enhancements (SPIFFENA).
– Clear the FIFO Flags (TXFFINTCLR, RXFFOVFCLR, and RXFFINTCLR).
– Release transmit and receive FIFO resets (TXFIFO and RXFIFORESET).
– Release SPI FIFO channels from reset (SPIRST).
Step 3. If interrupts are used:
• In non-FIFO mode, enable the receiver overrun and/or SPI interrupts (OVERRUNINTENA
and SPIINTENA).
• In FIFO mode, set the transmit and receive interrupt levels (TXFFIL and RXFFIL) then
enable the interrupts (TXFFIENA and RXFFIENA).
Step 4. Set SPISWRESET to 1 to release the SPI from the reset state.
NOTE: Do not change the SPI configuration when communication is in progress.
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