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SPI Registers
569
SPRUI07–March 2020
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Serial Peripheral Interface (SPI)
Table 9-9. SPISTS Register Field Descriptions (continued)
Bit Field Type Reset Description
6 INT_FLAG RC 0h
SPI Interrupt Flag
SPI INT FLAG is a read-only flag. Hardware sets this bit to indicate
that the SPI has completed sending or receiving the last bit and is
ready to be serviced. This flag causes an interrupt to be requested if
the SPI INT ENA bit (SPICTL.0) is set. The received character is
placed in the receiver buffer at the same time this bit is set. This bit
is cleared in one of three ways:
- Reading SPIRXBUF
- Writing a 0 to SPI SW RESET (SPICCR.7)
- Resetting the system
Note: This bit should not be used if FIFO mode is enabled. The
internal process of copying the received word from SPIRXBUF to the
Receive FIFO will clear this bit. Use the FIFO status, or FIFO
interrupt bits for similar functionality.
Reset type: SYSRSn
0h (R/W) = No full words have been received or transmitted.
1h (R/W) = Indicates that the SPI has completed sending or
receiving the last bit and is ready to be serviced.
5 BUFFULL_FLAG R 0h
SPI Transmit Buffer Full Flag
This read-only bit gets set to 1 when a character is written to the SPI
Transmit buffer SPITXBUF. It is cleared when the character is
automatically loaded into SPIDAT when the shifting out of a previous
character is complete.
Reset type: SYSRSn
0h (R/W) = Transmit buffer is not full.
1h (R/W) = Transmit buffer is full.
4-0 RESERVED R 0h
Reserved
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