SPI Registers
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SPRUI07–March 2020
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Serial Peripheral Interface (SPI)
Table 9-15. SPIFFTX Register Field Descriptions (continued)
Bit Field Type Reset Description
4-0 TXFFIL R/W 0h
Transmit FIFO Interrupt Level Bits
Transmit FIFO will generate interrupt when the FIFO status bits
(TXFFST4-0) and FIFO level bits (TXFFIL4-0 ) match (less than or
equal to).
Reset type: SYSRSn
0h (R/W) = A TX FIFO interrupt request is generated when there
are no words remaining in the TX buffer.
1h (R/W) = A TX FIFO interrupt request is generated when there is
1 word or no words remaining in the TX buffer.
2h (R/W) = A TX FIFO interrupt request is generated when there is
2 words or fewer remaining in the TX buffer.
10h (R/W) = A TX FIFO interrupt request is generated when there
are 16 words or fewer remaining in the TX buffer.
1Fh (R/W) = Reserved.
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