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SCI Registers
611
SPRUI07–March 2020
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Serial Communications Interface (SCI)
Table 10-16. SCIFFTX Register Field Descriptions (continued)
Bit Field Type Reset Description
6 TXFFINTCLR R-0/W1S 0h
Transmit FIFO clear
Reset type: SYSRSn
0h (R/W) = Write 0 has no effect on TXFIFINT flag bit, Bit reads
back a zero
1h (R/W) = Write 1 to clear TXFFINT flag in bit 7
5 TXFFIENA R/W 0h
Transmit FIFO interrrupt enable
Reset type: SYSRSn
0h (R/W) = TX FIFO interrupt is disabled
1h (R/W) = TX FIFO interrupt is enabled. This interrupt is triggered
whenever the transmit FIFO status (TXFFST) bits match (equal to
or less than) the interrupt trigger level bits TXFFIL (bits 4-0).
4-0 TXFFIL R/W 0h
TXFFIL4-0 Transmit FIFO interrupt level bits.
The transmit FIFO generates an interrupt whenever the FIFO status
bits (TXFFST4-0) are less than or equal to the FIFO level bits
(TXFFIL4-0). The maximum value that can be assigned to these bits
to generate an interrupt cannot be more than the depth of the TX
FIFO. The default value of these bits after reset is 00000b. Users
should set TXFFIL to best fit their application needs by weighing
between the CPU overhead to service the ISR and the best possible
usage of SCI bus bandwidth.
Reset type: SYSRSn
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