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SCI Registers
613
SPRUI07–March 2020
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Serial Communications Interface (SCI)
Table 10-17. SCIFFRX Register Field Descriptions (continued)
Bit Field Type Reset Description
7 RXFFINT R 0h
Receive FIFO interrupt
Reset type: SYSRSn
0h (R/W) = RXFIFO interrupt has not occurred, read-only bit
1h (R/W) = RXFIFO interrupt has occurred, read-only bit
6 RXFFINTCLR W 0h
Receive FIFO interrupt clear
Reset type: SYSRSn
0h (R/W) = Write 0 has no effect on RXFIFINT flag bit. Bit reads
back a zero.
1h (R/W) = Write 1 to clear RXFFINT flag in bit 7
5 RXFFIENA R/W 0h
Receive FIFO interrupt enable
Reset type: SYSRSn
0h (R/W) = RX FIFO interrupt is disabled
1h (R/W) = RX FIFO interrupt is enabled. This interrupt is triggered
whenever the receive FIFO status (RXFFST) bits match (equal to
or greater than) the interrupt trigger level bits RXFFIL (bits 4-0).
4-0 RXFFIL R/W 1Fh
Receive FIFO interrupt level bits
The receive FIFO generates an interrupt whenever the FIFO status
bits (RXFFST4-0) are greater than or equal to the FIFO level bits
(RXFFIL4-0). The maximum value that can be assigned to these bits
to generate an interrupt cannot be more than the depth of the RX
FIFO. The default value of these bits after reset is 11111b. Users
should set RXFFIL to best fit their application needs by weighing
between the CPU overhead to service the ISR and the best possible
usage of received SCI data.
Reset type: SYSRSn
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