I2C Registers
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SPRUI07–March 2020
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Inter-Integrated Circuit Module (I2C)
Table 11-23. I2CFFTX Register Field Descriptions (continued)
Bit Field Type Reset Description
4-0 TXFFIL R/W 0h
Transmit FIFO interrupt level.
These bits set the status level that will set the transmit interrupt flag.
When the TXFFST4-0 bits reach a value equal to or less than these
bits, the TXFFINT flag will be set. This will generate an interrupt if
the TXFFIENA bit is set. Because the I2C on this device has a 16-
level transmit FIFO, these bits cannot be configured for an interrupt
of more than 16 FIFO levels.
Reset type: SYSRSn
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