Overview
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
12.1 Overview
This device provides up to two high-speed multichannel buffered serial ports (McBSPs) that allow direct
interface to codecs and other devices in a system. The McBSP consists of a data-flow path and a control
path connected to external devices by six pins as shown in Figure 12-1.
Data is communicated to devices interfaced with the McBSP via the data transmit (DX) pin for
transmission and via the data receive (DR) pin for reception. Control information in the form of clocking
and frame synchronization is communicated via the following pins: CLKX (transmit clock), CLKR (receive
clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization).
The CPU and the DMA controller communicate with the McBSP through 16-bit wide registers accessible
via the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the
data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to the DX pin via the
transmit shift registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift
registers (RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the
receive buffer registers (RBRs) is then copied to the data receive registers (DRRs), which can be read by
the CPU or the DMA controller. This allows simultaneous movement of internal and external data
communications.
If the serial word length is 8 bits, 12 bits, or 16 bits, the DRR2, RBR2, RSR2, DXR2, and XSR2 registers
are not used (written, read, or shifted) For larger word lengths, these registers are needed to hold the
most significant bits.
The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and
FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads;
instead of the CLKR and FSR pins.
12.1.1 Features of the McBSPs
The McBSPs feature:
• Full-duplex communication
• Double-buffered transmission and triple-buffered reception, allowing a continuous data stream
• Independent clocking and framing for reception and transmission
• The capability to send interrupts to the CPU and to send DMA events to the DMA controller
• 128 channels for transmission and reception
• Multichannel selection modes that enable or disable block transfers in each of the channels
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected A/D and D/A devices
• Support for external generation of clock signals and frame-synchronization signals
• A programmable sample rate generator for internal generation and control of clock signals and frame-
synchronization signals
• Programmable polarity for frame-synchronization pulses and clock signals
• Direct interface to:
– T1/E1 framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multiphase frame capability is provided)
– I2S compliant devices
– SPI devices
• A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits
NOTE: A value of the chosen data size is referred to as a serial word or word throughout the
McBSP documentation. Elsewhere, word is used to describe a 16-bit value.
• μ-law and A-law companding
• The option of transmitting/receiving 8-bit data with the LSB first
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