Clocking and System Control
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SPRUI07–March 2020
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System Control and Interrupts
When the VCOCLK counter overflows, the missing clock detection logic resets the CPU, peripherals, and
other device logic. The reset generated is known as a missing clock detect logic reset (MCLKRES). The
MCLKRES is an internal reset only. The external XRS pin of the device is not pulled low by MCLKRES
and the PLLCR and PLLSTS registers are not reset.
In addition to resetting the device, the missing oscillator logic sets the PLLSTS[MCLKSTS] register bit.
When the MCLKCSTS bit is 1, this indicates that the missing oscillator detect logic reset the part and that
the CPU is now running either at or one-half of the limp mode frequency.
Software should check the PLLSTS[MCLKSTS] bit after a reset to determine if the device was reset by
MCLKRES due to a missing clock condition. If MCLKSTS is set, then the firmware should take the action
appropriate for the system such as a system shutdown. The missing clock status can be cleared by writing
a 1 to the PLLSTS[MCLKCLR] bit. This will reset the missing clock detection circuits and counters. If
OSCCLK is still missing after writing to the MCLKCLR bit, then the VCOCLK counter again overflows and
the process will repeat.
NOTE: Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSP will be held in reset should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the flash memory and the V
DD3VFL
rail.
The following precautions and limitations should be kept in mind:
• Use the proper procedure when changing the PLL Control Register.
Always follow the procedure outlined in Figure 1-22 when modifying the PLLCR register.
• Do not write to the PLLCR register when the device is operating in limp mode.
When writing to the PLLCR register, the device switches to the CPU's CLKIN input to OSCCLK/2.
When operating after limp mode has been detected, OSCCLK may not be present and the clocks to
the system will stop. Always check that the PLLSTS[MCLKSTS] bit = 0 before writing to the PLLCR
register as described in Figure 1-22.
• The watchdog is not functional without an external clock.
The watchdog is not functional and cannot generate a reset when OSCCLK is not present. No special
hardware has been added to switch the watchdog to the limp mode clock should OSCCLK become
missing.
• Limp mode may not work from power up.
The PLL may not generate a limp mode clock if OSCCLK is missing from power-up. Only if OSCCLK is
initially present will a limp mode clock be generated by the PLL.
• Do not enter HALT low power mode when the device is operating in limp mode.
If you try to enter HALT mode when the device is already operating in limp mode then the device may
not properly enter HALT. The device may instead enter STANDBY mode or may hang and you may
not be able to exit HALT mode. For this reason, always check that the PLLSTS[MCLKSTS] bit = 0
before entering HALT mode.
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