Clocking and System Control
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SPRUI07–March 2020
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System Control and Interrupts
1.3.2.4 PLL Control (PLLCR) Register
The PLLCR register is used to change the PLL multiplier of the device. Before writing to the PLLCR
register, the following requirements must be met:
• The PLLSTS[DIVSEL] bit must be 0 (CLKIN divide by 4 enabled). Change PLLSTS[DIVSEL] only after
the PLL has completed locking, that is, after PLLSTS[PLLLOCKS] = 1.
• The device must not be operating in "limp mode". That is, the PLLSTS[MCLKSTS] bit must be 0.
Once the PLL is stable and has locked at the new specified frequency, the PLL switches CLKIN to the
new value as shown in Table 1-21. When this happens, the PLLLOCKS bit in the PLLSTS register is set,
indicating that the PLL has finished locking and the device is now running at the new frequency. User
software can monitor the PLLLOCKS bit to determine when the PLL has completed locking. Once
PLLSTS[PLLLOCKS] = 1, DIVSEL can be changed.
Follow the procedure in Figure 1-22 any time you are writing to the PLLCR register.
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