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eCAN Registers
819
SPRUI07–March 2020
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Controller Area Network (CAN)
Table 13-22. Global Interrupt Flag Registers (CANGIF0/CANGIF1) Field Descriptions (continued)
Bit Field Value Description
16 TCOF0/1 Time stamp counter overflow flag.
1 The MSB of the time stamp counter has changed from 0 to 1.
0 The MSB of the time stamp counter is 0. That is, it has not changed from 0 to 1.
15 GMIF0/1 Global mailbox interrupt flag. This bit is set only when the corresponding mailbox interrupt mask bit
in the CANMIM register is set.
1 One of the mailboxes transmitted or received a message successfully.
0 No message has been transmitted or received.
14 AAIF0/1 Abort-acknowledge interrupt flag
1 A send transmission request has been aborted.
0 No transmission has been aborted.
Note: The AAIFn bit is cleared by clearing the set AAn bit.
13 WDIF0/WDIF1 Write-denied interrupt flag
1 The CPU write access to a mailbox was not successful. The WDIF interrupt is asserted when the
identifier field of a mailbox is written to, while it is enabled. Before writing to the MSGID field of a
MBX, it should be disabled. If you try this operation when the MBX is still enabled, the WDIF bit will
be set and a CAN interrupt asserted.
0 The CPU write access to the mailbox was successful.
12 WUIF0/WUIF1 Wake-up interrupt flag
1 During local power down, this flag indicates that the module has left sleep mode.
0 The module is still in sleep mode or normal operation
11 RMLIF0/1 Receive-message-lost interrupt flag
1 At least for one of the receive mailboxes, an overflow condition has occurred and the corresponding
bit in the MILn register is cleared.
0 No message has been lost.
Note: The RMLIFn bit is cleared by clearing the set RMPn bit.
10 BOIF0/BOIF1 Bus off interrupt flag
1 The CAN module has entered bus-off mode.
0 The CAN module is still in bus-on mode.
9 EPIF0/EPIF1 Error passive interrupt flag
1 The CAN module has entered error-passive mode.
0 The CAN module is not in error-passive mode.
8 WLIF0/WLIF1 Warning level interrupt flag
1 At least one of the error counters has reached the warning level.
0 None of the error counters has reached the warning level.
7:5 Reserved Reads are undefined and writes have no effect.
4:0 MIV0.4:0/MIV1.4:
0
Mailbox interrupt vector. Only bits 3:0 are available in SCC mode.
This vector indicates the number of the mailbox that set the global mailbox interrupt flag. It keeps
that vector until the appropriate MIFn bit is cleared or when a higher priority mailbox interrupt
occurred. Then the highest interrupt vector is displayed, with mailbox 31 having the highest priority.
In the SCC mode, mailbox 15 has the highest priority. Mailboxes 16 to 31 are not recognized.
If no flag is set in the TA/RMP register and GMIF1 or GMIF0 also cleared, this value is undefined.
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