General-Purpose Input/Output (GPIO)
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SPRUI07–March 2020
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System Control and Interrupts
Table 1-41. GPIO Data Registers (continued)
Name Address Size (x16) Register Description Bit Description
GPBTOGGLE 0x6FCE 2 GPIO B Toggle Register (GPIO32-GPIO63) Figure 1-69
GPCDAT 0x6FD0 2 GPIO C Data Register (GPIO64 - GPIO87) Figure 1-67
GPCSET 0x6FD2 2 GPIO C Set Register (GPIO64 - GPIO87) Figure 1-70
GPCCLEAR 0x6FD4 2 GPIO C Clear Register (GPIO64 - GPIO87) Figure 1-70
GPCTOGGLE 0x6FD6 2 GPIO C Toggle Register (GPIO64 - GPIO87) Figure 1-70
• GPxDAT Registers
Each I/O port has one data register. Each bit in the data register corresponds to one GPIO pin. No
matter how the pin is configured (GPIO or peripheral function), the corresponding bit in the data
register reflects the current state of the pin after qualification. Writing to the GPxDAT register clears or
sets the corresponding output latch and if the pin is enabled as a general purpose output (GPIO
output) the pin will also be driven either low or high. If the pin is not configured as a GPIO output then
the value will be latched, but the pin will not be driven. Only if the pin is later configured as a GPIO
output, will the latched value be driven onto the pin.
When using the GPxDAT register to change the level of an output pin, you should be cautious not to
accidentally change the level of another pin. For example, if you mean to change the output latch level
of GPIOA0 by writing to the GPADAT register bit 0, using a read-modify-write instruction. The problem
can occur if another I/O port A signal changes level between the read and the write stage of the
instruction. You can also change the state of that output latch. You can avoid this scenario by using
the GPxSET, GPxCLEAR, and GPxTOGGLE registers to load the output latch instead.
• GPxSET Registers
The set registers are used to drive specified GPIO pins high without disturbing other pins. Each I/O
port has one set register and each bit corresponds to one GPIO pin. The set registers always read
back 0. If the corresponding pin is configured as an output, then writing a 1 to that bit in the set register
will set the output latch high and the corresponding pin will be driven high. If the pin is not configured
as a GPIO output, then the value will be latched but the pin will not be driven. Only if the pin is later
configured as a GPIO output will the latched value will be driven onto the pin. Writing a 0 to any bit in
the set registers has no effect.
• GPxCLEAR Registers
The clear registers are used to drive specified GPIO pins low without disturbing other pins. Each I/O
port has one clear register. The clear registers always read back 0. If the corresponding pin is
configured as a general purpose output, then writing a 1 to the corresponding bit in the clear register
will clear the output latch and the pin will be driven low. If the pin is not configured as a GPIO output,
then the value will be latched but the pin will not be driven. Only if the pin is later configured as a GPIO
output will the latched value will be driven onto the pin. Writing a 0 to any bit in the clear registers has
no effect.
• GPxTOGGLE Registers
The toggle registers are used to drive specified GPIO pins to the opposite level without disturbing other
pins. Each I/O port has one toggle register. The toggle registers always read back 0. If the
corresponding pin is configured as an output, then writing a 1 to that bit in the toggle register flips the
output latch and pulls the corresponding pin in the opposite direction. That is, if the output pin is driven
low, then writing a 1 to the corresponding bit in the toggle register will pull the pin high. Likewise, if the
output pin is high, then writing a 1 to the corresponding bit in the toggle register will pull the pin low. If
the pin is not configured as a GPIO output, then the value will be latched but the pin will not be driven.
Only if the pin is later configured as a GPIO output will the latched value will be driven onto the pin.
Writing a 0 to any bit in the toggle registers has no effect.
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