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General-Purpose Input/Output (GPIO)
103
SPRUI07–March 2020
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System Control and Interrupts
Table 1-49. GPIOC MUX
Default at Reset
Primary I/O Function Peripheral Selection 2 or 3
GPCMUX1 Register Bits (GPCMUX1 bits = 00 or 01) (GPCMUX1 bits = 10 or 11)
1,0 GPIO64 (I/O) XD15 (I/O)
3,2 GPIO65 (I/O) XD14 (I/O)
5,4 GPIO66 (I/O) XD13 (I/O)
7,6 GPIO67 (I/O) XD12 (I/O)
9,8 GPIO68 (I/O) XD11 (I/O)
11,10 GPIO69 (I/O) XD10 (I/O)
13,12 GPIO70 (I/O) XD9 (I/O)
15,14 GPIO71 (I/O) XD8 (I/O)
17,16 GPIO72 (I/O) XD7 (I/O)
19,18 GPIO73 (I/O) XD6 (I/O)
21,20 GPIO74 (I/O) XD5 (I/O)
23,22 GPIO75 (I/O) XD4 (I/O)
25,24 GPIO76 (I/O) XD3 (I/O)
27,26 GPIO77 (I/O) XD2 (I/O)
29,28 GPIO78 (I/O) XD1 (I/O)
31,30 GPIO79 (I/O) XD0 (I/O)
GPCMUX2 Register Bits GPCMUX2 bits = 00 or 01 GPCMUX2 bits = 10 or 11
1,0 GPIO80 (I/O) XA8 (O)
3,2 GPIO81 (I/O) XA9 (O)
5,4 GPIO82 (I/O) XA10 (O)
7,6 GPIO83 (I/O) XA11 (O)
9,8 GPIO84 (I/O) XA12 (O)
11,10 GPIO85 (I/O) XA13 (O)
13,12 GPIO86 (I/O) XA14 (O)
15,14 GPIO87 (I/O) XA15 (O)
16 – 31 Reserved Reserved
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