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SPRUI07–March 2020
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List of Tables
List of Tables
1-1. Flash/OTP Configuration Registers...................................................................................... 44
1-2. Flash Options Register (FOPT) Field Descriptions .................................................................... 45
1-3. Flash Power Register (FPWR) Field Descriptions ..................................................................... 45
1-4. Flash Status Register (FSTATUS) Field Descriptions................................................................. 46
1-5. Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions ................................................... 47
1-6. Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions............................. 47
1-7. Flash Wait-State Register (FBANKWAIT) Field Descriptions ........................................................ 48
1-8. OTP Wait-State Register (FOTPWAIT) Field Descriptions ........................................................... 49
1-9. Security Levels ............................................................................................................. 50
1-10. Resources Affected by the CSM ......................................................................................... 52
1-11. Resources Not Affected by the CSM .................................................................................... 52
1-12. Code Security Module (CSM) Registers ................................................................................ 53
1-13. CSM Status and Control Register (CSMSCR) Field Descriptions ................................................... 54
1-14. PLL, Clocking, Watchdog, and Low-Power Mode Registers ........................................................ 60
1-15. Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions................................................ 60
1-16. Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions ............................................... 62
1-17. Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions................................................ 64
1-18. High-Speed Peripheral Clock Prescaler (HISPCP) Field Descriptions.............................................. 65
1-19. Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions................................... 65
1-20. Possible PLL Configuration Modes ...................................................................................... 67
1-21. PLLCR Bit Descriptions ................................................................................................... 72
1-22. PLL Status Register (PLLSTS) Field Descriptions..................................................................... 73
1-23. Low-Power Mode Summary .............................................................................................. 74
1-24. Low Power Modes ......................................................................................................... 74
1-25. Low Power Mode Control 0 Register (LPMCR0) Field Descriptions ................................................ 75
1-26. Example Watchdog Key Sequences..................................................................................... 77
1-27. System Control and Status Register (SCSR) Field Descriptions .................................................... 79
1-28. Watchdog Counter Register (WDCNTR) Field Descriptions ......................................................... 80
1-29. Watchdog Reset Key Register (WDKEY) Field Descriptions......................................................... 80
1-30. Watchdog Control Register (WDCR) Field Descriptions.............................................................. 80
1-31. CPU Timers 0, 1, 2 Configuration and Control Registers............................................................. 82
1-32. TIMERxTIM Register Field Descriptions ................................................................................ 83
1-33. TIMERxTIMH Register Field Descriptions .............................................................................. 83
1-34. TIMERxPRD Register Field Descriptions ............................................................................... 83
1-35. TIMERxPRDH Register Field Descriptions ............................................................................. 83
1-36. TIMERxTCR Register Field Descriptions ............................................................................... 84
1-37. TIMERxTPR Register Field Descriptions ............................................................................... 85
1-38. TIMERxTPRH Register Field Descriptions.............................................................................. 85
1-39. GPIO Control Registers ................................................................................................... 92
1-40. GPIO Interrupt and Low Power Mode Select Registers............................................................... 92
1-41. GPIO Data Registers ...................................................................................................... 93
1-42. Sampling Period............................................................................................................ 96
1-43. Sampling Frequency....................................................................................................... 96
1-44. Case 1: Three-Sample Sampling Window Width ...................................................................... 97
1-45. Case 2: Six-Sample Sampling Window Width.......................................................................... 97
1-46. Default State of Peripheral Input........................................................................................ 100
1-47. GPIOA MUX............................................................................................................... 101
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