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SPRUI07–March 2020
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List of Tables
1-48. GPIOB MUX............................................................................................................... 102
1-49. GPIOC MUX............................................................................................................... 103
1-50. GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions............................................. 104
1-51. GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions ..................................................... 106
1-52. GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions ..................................................... 108
1-53. GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions ..................................................... 110
1-54. GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions..................................................... 112
1-55. GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions..................................................... 113
1-56. GPIO Port A Qualification Control (GPACTRL) Register Field Descriptions ..................................... 115
1-57. GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions ..................................... 116
1-58. GPIO Port A Qualification Select 1 (GPAQSEL1) Register Field Descriptions................................... 117
1-59. GPIO Port A Qualification Select 2 (GPAQSEL2) Register Field Descriptions................................... 117
1-60. GPIO Port B Qualification Select 1 (GPBQSEL1) Register Field Descriptions................................... 118
1-61. GPIO Port B Qualification Select 2 (GPBQSEL2) Register Field Descriptions................................... 118
1-62. GPIO Port A Direction (GPADIR) Register Field Descriptions...................................................... 119
1-63. GPIO Port B Direction (GPBDIR) Register Field Descriptions...................................................... 119
1-64. GPIO Port C Direction (GPCDIR) Register Field Descriptions ..................................................... 120
1-65. GPIO Port A Internal Pullup Disable (GPAPUD) Register Field Descriptions .................................... 120
1-66. GPIO Port B Internal Pullup Disable (GPBPUD) Register Field Descriptions .................................... 121
1-67. GPIO Port C Internal Pullup Disable (GPCPUD) Register Field Descriptions.................................... 121
1-68. GPIO Port A Data (GPADAT) Register Field Descriptions.......................................................... 122
1-69. GPIO Port B Data (GPBDAT) Register Field Descriptions.......................................................... 123
1-70. GPIO Port C Data (GPCDAT) Register Field Descriptions ......................................................... 123
1-71. GPIO Port A Set (GPASET) Register Field Descriptions............................................................ 124
1-72. GPIO Port A Clear (GPACLEAR) Register Field Descriptions ..................................................... 124
1-73. GPIO Port A Toggle (GPATOGGLE) Register Field Descriptions ................................................. 124
1-74. GPIO Port B Set (GPBSET) Register Field Descriptions............................................................ 125
1-75. GPIO Port B Clear (GPBCLEAR) Register Field Descriptions ..................................................... 125
1-76. GPIO Port B Toggle (GPBTOGGLE) Register Field Descriptions ................................................. 125
1-77. GPIO Port C Set (GPCSET) Register Field Descriptions ........................................................... 126
1-78. GPIO Port C Clear (GPCCLEAR) Register Field Descriptions ..................................................... 126
1-79. GPIO Port C Toggle (GPCTOGGLE) Register Field Descriptions ................................................. 126
1-80. GPIO XINTn Interrupt Select (GPIOXINTnSEL) Register Field Descriptions..................................... 127
1-81. XINT1/XINT2 Interrupt Select and Configuration Registers......................................................... 127
1-82. GPIO XINT3 - XINT7 Interrupt Select (GPIOXINTnSEL) Register Field Descriptions .......................... 127
1-83. XINT3 - XINT7 Interrupt Select and Configuration Registers....................................................... 127
1-84. GPIO XNMI Interrupt Select (GPIOXNMISEL) Register Field Descriptions ...................................... 128
1-85. GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register Field Descriptions.......................... 128
1-86. Peripheral Frame 0 Registers .......................................................................................... 129
1-87. Peripheral Frame 1 Registers........................................................................................... 129
1-88. Peripheral Frame 2 Registers........................................................................................... 130
1-89. Peripheral Frame 3 Registers........................................................................................... 130
1-90. Access to EALLOW-Protected Registers.............................................................................. 131
1-91. EALLOW-Protected Device Emulation Registers..................................................................... 131
1-92. EALLOW-Protected Flash/OTP Configuration Registers............................................................ 131
1-93. EALLOW-Protected Code Security Module (CSM) Registers ...................................................... 132
1-94. EALLOW-Protected PIE Vector Table ................................................................................. 132
1-95. EALLOW-Protected PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................... 133
1-96. EALLOW-Protected GPIO MUX Registers ........................................................................... 133
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