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SPRUI07–March 2020
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List of Tables
1-97. EALLOW-Protected eCAN Registers .................................................................................. 134
1-98. EALLOW-Protected ePWM1 - ePWM6 Registers.................................................................... 134
1-99. XINTF Registers ......................................................................................................... 134
1-100. Device Emulation Registers ............................................................................................. 135
1-101. DEVICECNF Register Field Descriptions.............................................................................. 135
1-102. PARTID Register Field Descriptions ................................................................................... 136
1-103. CLASSID Register Description.......................................................................................... 136
1-104. REVID Register Field Descriptions..................................................................................... 136
1-105. PROTSTART and PROTRANGE Registers........................................................................... 137
1-106. PROTSTART Valid Values ............................................................................................. 137
1-107. PROTRANGE Valid Values ............................................................................................. 138
1-108. Enabling Interrupt......................................................................................................... 140
1-109. Interrupt Vector Table Mapping ........................................................................................ 141
1-110. Vector Table Mapping After Reset Operation ........................................................................ 141
1-111. PIE MUXed Peripheral Interrupt Vector Table ........................................................................ 149
1-112. PIE Vector Table.......................................................................................................... 150
1-113. PIE Configuration and Control Registers .............................................................................. 153
1-114. PIE Control Register (PIECTRL) Field Descriptions ................................................................. 154
1-115. PIE Interrupt Acknowledge Register (PIEACK) Field Descriptions................................................. 154
1-116. PIE Interrupt Enable Register (PIEIERx) Field Descriptions........................................................ 155
1-117. PIE Interrupt Flag Register (PIEIFRx) Field Descriptions ........................................................... 156
1-118. Interrupt Flag Register (IFR) — CPU Register Field Descriptions ................................................. 157
1-119. Interrupt Enable Register (IER) — CPU Register Field Descriptions.............................................. 159
1-120. Debug Interrupt Enable Register (DBGIER) — CPU Register Field Descriptions ............................... 161
1-121. External Interrupt n Control Register (XINTnCR) Field Descriptions .............................................. 163
1-122. External NMI Interrupt Control Register (XNMICR) Field Descriptions............................................ 164
1-123. XNMICR Register Settings and Interrupt Sources ................................................................... 164
1-124. External Interrupt 1 Counter (XINT1CTR) Field Descriptions....................................................... 164
1-125. External Interrupt 2 Counter (XINT2CTR) Field Descriptions....................................................... 165
1-126. External NMI Interrupt Counter (XNMICTR) Field Descriptions .................................................... 165
2-1. Vector Locations .......................................................................................................... 171
2-2. Configuration for Device Modes ........................................................................................ 173
2-3. Boot Mode Selection ..................................................................................................... 175
2-4. General Structure of Source Program Data Stream in 16-Bit Mode ............................................... 180
2-5. LSB/MSB Loading Sequence in 8-bit Data Stream .................................................................. 181
2-6. Pins Used by the McBSP Loader....................................................................................... 188
2-7. Bit-Rate Values for Different XCLKIN Values......................................................................... 188
2-8. McBSP 16-Bit Data Stream ............................................................................................. 188
2-9. Parallel GPIO Boot 16-Bit Data Stream ............................................................................... 192
2-10. Parallel GPIO Boot 8-Bit Data Stream ................................................................................. 192
2-11. XINTF Parallel Boot 16-Bit Data Stream .............................................................................. 198
2-12. XINTF Parallel Boot 8-Bit Data Stream................................................................................ 199
2-13. SPI 8-Bit Data Stream ................................................................................................... 204
2-14. I2C 8-Bit Data Stream.................................................................................................... 209
2-15. Bit-Rate Values for Different XCLKIN Values......................................................................... 210
2-16. eCAN 8-Bit Data Stream................................................................................................. 211
2-17. CPU Register Restored Values......................................................................................... 213
2-18. Bootloader Options ....................................................................................................... 214
2-19. Bootloader Revision and Checksum Information..................................................................... 217
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