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SPRUI07–March 2020
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List of Tables
10-18. SCIFFCT Register Field Descriptions.................................................................................. 614
10-19. SCIPRI Register Field Descriptions .................................................................................... 615
11-1. Dependency of Delay d on the Divide-Down Value IPSC........................................................... 620
11-2. Operating Modes of the I2C Module ................................................................................... 621
11-3. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR................ 622
11-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR ............................ 625
11-5. Ways to Generate a NACK Bit.......................................................................................... 626
11-6. Descriptions of the Basic I2C Interrupt Requests .................................................................... 629
11-7. I2C Base Address Table................................................................................................. 632
11-8. I2C_REGS Registers..................................................................................................... 633
11-9. I2C_REGS Access Type Codes ........................................................................................ 633
11-10. I2COAR Register Field Descriptions ................................................................................... 634
11-11. I2CIER Register Field Descriptions .................................................................................... 635
11-12. I2CSTR Register Field Descriptions.................................................................................... 636
11-13. I2CCLKL Register Field Descriptions .................................................................................. 640
11-14. I2CCLKH Register Field Descriptions.................................................................................. 641
11-15. I2CCNT Register Field Descriptions ................................................................................... 642
11-16. I2CDRR Register Field Descriptions ................................................................................... 643
11-17. I2CSAR Register Field Descriptions ................................................................................... 644
11-18. I2CDXR Register Field Descriptions ................................................................................... 645
11-19. I2CMDR Register Field Descriptions................................................................................... 646
11-20. I2CISRC Register Field Descriptions .................................................................................. 650
11-21. I2CEMDR Register Field Descriptions ................................................................................. 651
11-22. I2CPSC Register Field Descriptions ................................................................................... 652
11-23. I2CFFTX Register Field Descriptions .................................................................................. 653
11-24. I2CFFRX Register Field Descriptions.................................................................................. 655
12-1. McBSP Interface Pins/Signals .......................................................................................... 659
12-2. Register Bits That Determine the Number of Phases, Words, and Bits........................................... 666
12-3. Interrupts and DMA Events Generated by a McBSP ................................................................ 670
12-4. Effects of DLB and CLKSTP on Clock Modes ........................................................................ 672
12-5. Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits ................ 672
12-6. Polarity Options for the Input to the Sample Rate Generator....................................................... 673
12-7. Input Clock Selection for Sample Rate Generator ................................................................... 676
12-8. Block - Channel Assignment ............................................................................................ 685
12-9. 2-Partition Mode .......................................................................................................... 686
12-10. 8-Partition mode .......................................................................................................... 686
12-11. Receive Channel Assignment and Control With Eight Receive Partitions ........................................ 688
12-12. Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used......................... 689
12-13. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits ......................................... 690
12-14. Bits Used to Enable and Configure the Clock Stop Mode........................................................... 693
12-15. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme................................................... 694
12-16. Bit Values Required to Configure the McBSP as an SPI Master .................................................. 697
12-17. Bit Values Required to Configure the McBSP as an SPI Slave .................................................... 698
12-18. Register Bits Used to Reset or Enable the McBSP Receiver Field Descriptions ................................ 700
12-19. Reset State of Each McBSP Pin........................................................................................ 700
12-20. Register Bit Used to Enable/Disable the Digital Loopback Mode .................................................. 701
12-21. Receive Signals Connected to Transmit Signals in Digital Loopback Mode...................................... 701
12-22. Register Bits Used to Enable/Disable the Clock Stop Mode........................................................ 701
12-23. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme................................................... 702
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